Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2009-2018, Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2018-2020, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* PHY register and bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PHY_CTRL_COMMON0		0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SIDDQ				BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PHY_IRQ_CMD			0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PHY_INTR_MASK0			0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PHY_INTR_CLEAR0			0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DPDM_MASK			0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DP_1_0				BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DP_0_1				BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DM_1_0				BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DM_0_1				BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) enum hsphy_voltage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	VOL_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	VOL_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	VOL_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	VOL_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) enum hsphy_vreg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	VDD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	VDDA_1P8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	VDDA_3P3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	VREG_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct hsphy_init_seq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct hsphy_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	const struct hsphy_init_seq *init_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int init_seq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct hsphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct reset_control *phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct reset_control *por_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct regulator_bulk_data vregs[VREG_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	const struct hsphy_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	enum phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 				    int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	priv->mode = PHY_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (mode > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		priv->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* Clear any existing interrupts before enabling the interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	val = readb(priv->base + PHY_INTR_CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	val |= DPDM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	writeb(val, priv->base + PHY_INTR_CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	writeb(0x0, priv->base + PHY_IRQ_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	usleep_range(200, 220);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	writeb(0x1, priv->base + PHY_IRQ_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* Make sure the interrupts are cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	usleep_range(200, 220);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	val = readb(priv->base + PHY_INTR_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (priv->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case PHY_MODE_USB_HOST_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case PHY_MODE_USB_HOST_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case PHY_MODE_USB_DEVICE_HS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case PHY_MODE_USB_DEVICE_FS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		val |= DP_1_0 | DM_0_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case PHY_MODE_USB_HOST_LS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case PHY_MODE_USB_DEVICE_LS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		val |= DP_0_1 | DM_1_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		/* No device connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		val |= DP_0_1 | DM_0_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writeb(val, priv->base + PHY_INTR_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	val = readb(priv->base + PHY_INTR_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	val &= ~DPDM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	writeb(val, priv->base + PHY_INTR_MASK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	val = readb(priv->base + PHY_INTR_CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	val |= DPDM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	writeb(val, priv->base + PHY_INTR_CLEAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	writeb(0x0, priv->base + PHY_IRQ_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	usleep_range(200, 220);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	writeb(0x1, priv->base + PHY_IRQ_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	usleep_range(200, 220);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	val = readb(priv->base + PHY_CTRL_COMMON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	val |= SIDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	writeb(val, priv->base + PHY_CTRL_COMMON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	val = readb(priv->base + PHY_CTRL_COMMON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	val &= ~SIDDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	writeb(val, priv->base + PHY_CTRL_COMMON0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int qcom_snps_hsphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ret = regulator_bulk_enable(VREG_NUM, priv->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	qcom_snps_hsphy_disable_hv_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	qcom_snps_hsphy_exit_retention(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int qcom_snps_hsphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	qcom_snps_hsphy_enter_retention(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	qcom_snps_hsphy_enable_hv_interrupts(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	regulator_bulk_disable(VREG_NUM, priv->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int qcom_snps_hsphy_reset(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = reset_control_assert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	usleep_range(10, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ret = reset_control_deassert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	const struct hsphy_data *data = priv->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	const struct hsphy_init_seq *seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	/* Device match data is optional. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	seq = data->init_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	for (i = 0; i < data->init_seq_num; i++, seq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		writeb(seq->val, priv->base + seq->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (seq->delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			usleep_range(seq->delay, seq->delay + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = reset_control_assert(priv->por_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * The Femto PHY is POR reset in the following scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * 1. After overriding the parameter registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * 2. Low power mode exit from PHY retention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * Ensure that SIDDQ is cleared before bringing the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * out of reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	qcom_snps_hsphy_exit_retention(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * As per databook, 10 usec delay is required between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * PHY POR assert and de-assert.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ret = reset_control_deassert(priv->por_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * As per databook, it takes 75 usec for PHY to stabilize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * after the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int qcom_snps_hsphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ret = qcom_snps_hsphy_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		goto disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	qcom_snps_hsphy_init_sequence(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	ret = qcom_snps_hsphy_por_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		goto disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) disable_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int qcom_snps_hsphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct hsphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct phy_ops qcom_snps_hsphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.init = qcom_snps_hsphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.exit = qcom_snps_hsphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.power_on = qcom_snps_hsphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.power_off = qcom_snps_hsphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.set_mode = qcom_snps_hsphy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const char * const qcom_snps_hsphy_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	"ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	"ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	"sleep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int qcom_snps_hsphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct hsphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (!priv->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	for (i = 0; i < priv->num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		priv->clks[i].id = qcom_snps_hsphy_clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (IS_ERR(priv->phy_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return PTR_ERR(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	priv->por_reset = devm_reset_control_get_exclusive(dev, "por");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (IS_ERR(priv->por_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return PTR_ERR(priv->por_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	priv->vregs[VDD].supply = "vdd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	priv->vregs[VDDA_1P8].supply = "vdda1p8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	priv->vregs[VDDA_3P3].supply = "vdda3p3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	ret = devm_regulator_bulk_get(dev, VREG_NUM, priv->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	/* Get device match data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	priv->data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (IS_ERR(provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ret = regulator_set_load(priv->vregs[VDDA_1P8].consumer, 19000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	ret = regulator_set_load(priv->vregs[VDDA_3P3].consumer, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		goto unset_1p8_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unset_1p8_load:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	regulator_set_load(priv->vregs[VDDA_1P8].consumer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)  * The macro is used to define an initialization sequence.  Each tuple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)  * is meant to program 'value' into phy register at 'offset' with 'delay'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)  * in us followed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define HSPHY_INIT_CFG(o, v, d)	{ .offset = o, .val = v, .delay = d, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct hsphy_init_seq init_seq_femtophy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	HSPHY_INIT_CFG(0xc0, 0x01, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	HSPHY_INIT_CFG(0xe8, 0x0d, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	HSPHY_INIT_CFG(0x74, 0x12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	HSPHY_INIT_CFG(0x98, 0x63, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	HSPHY_INIT_CFG(0x9c, 0x03, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	HSPHY_INIT_CFG(0xa0, 0x1d, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	HSPHY_INIT_CFG(0xa4, 0x03, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	HSPHY_INIT_CFG(0x8c, 0x23, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	HSPHY_INIT_CFG(0x78, 0x08, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	HSPHY_INIT_CFG(0x7c, 0xdc, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	HSPHY_INIT_CFG(0x90, 0xe0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	HSPHY_INIT_CFG(0x74, 0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	HSPHY_INIT_CFG(0x90, 0x60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct hsphy_data hsphy_data_femtophy = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.init_seq = init_seq_femtophy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.init_seq_num = ARRAY_SIZE(init_seq_femtophy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct of_device_id qcom_snps_hsphy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	{ .compatible = "qcom,usb-hs-28nm-femtophy", .data = &hsphy_data_femtophy, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct platform_driver qcom_snps_hsphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	.probe = qcom_snps_hsphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.name = "qcom,usb-hs-28nm-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.of_match_table = qcom_snps_hsphy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) module_platform_driver(qcom_snps_hsphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_DESCRIPTION("Qualcomm 28nm Hi-Speed USB PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MODULE_LICENSE("GPL v2");