^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SLEEPM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OPMODE_MASK GENMASK(4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OPMODE_NORMAL (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OPMODE_NONDRIVING BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TERMSEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XCVRSEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define POR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RETENABLEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSEL_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FSEL_DEFAULT (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VBUSVLDEXTSEL0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLLBTUNE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VREGBYPASS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VBUSVLDEXT0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USB2_AUTO_RESUME BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USB2_SUSPEND_N BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB2_SUSPEND_N_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB2_PHY_USB_PHY_CFG0 (0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REFCLK_SEL_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REFCLK_SEL_DEFAULT (0x2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const char * const qcom_snps_hsphy_vreg_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "vdda-pll", "vdda33", "vdda18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * struct qcom_snps_hsphy - snps hs phy attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @phy: generic phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @base: iomapped memory space for snps hs phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @cfg_ahb_clk: AHB2PHY interface clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @ref_clk: phy reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @iface_clk: phy interface clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @phy_reset: phy reset control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @vregs: regulator supplies bulk data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @phy_initialized: if PHY has been initialized correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @mode: contains the current mode the PHY is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct qcom_snps_hsphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk *cfg_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct reset_control *phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool phy_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel_relaxed(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Ensure above write is completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (hsphy->mode == PHY_MODE_USB_HOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Enable auto-resume to meet remote wakeup timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) qcom_snps_hsphy_write_mask(hsphy->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) USB2_PHY_USB_PHY_HS_PHY_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) USB2_AUTO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) USB2_AUTO_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) qcom_snps_hsphy_write_mask(hsphy->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) USB2_PHY_USB_PHY_HS_PHY_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0, USB2_AUTO_RESUME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_disable_unprepare(hsphy->cfg_ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(&hsphy->phy->dev, "failed to enable cfg ahb clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!hsphy->phy_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) qcom_snps_hsphy_suspend(hsphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!hsphy->phy_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) qcom_snps_hsphy_resume(hsphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hsphy->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int qcom_snps_hsphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = clk_prepare_enable(hsphy->cfg_ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto poweroff_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = reset_control_assert(hsphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = reset_control_deassert(hsphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto disable_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) UTMI_PHY_CMN_CTRL_OVERRIDE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) UTMI_PHY_CMN_CTRL_OVERRIDE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) POR, POR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) qcom_snps_hsphy_write_mask(hsphy->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FSEL_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) qcom_snps_hsphy_write_mask(hsphy->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PLLBTUNE, PLLBTUNE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) qcom_snps_hsphy_write_mask(hsphy->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) VBUSVLDEXTSEL0, VBUSVLDEXTSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) VBUSVLDEXT0, VBUSVLDEXT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) qcom_snps_hsphy_write_mask(hsphy->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) VREGBYPASS, VREGBYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SLEEPM, SLEEPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) POR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) USB2_SUSPEND_N_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hsphy->phy_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) disable_ahb_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) clk_disable_unprepare(hsphy->cfg_ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) poweroff_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int qcom_snps_hsphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reset_control_assert(hsphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clk_disable_unprepare(hsphy->cfg_ahb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) hsphy->phy_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct phy_ops qcom_snps_hsphy_gen_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .init = qcom_snps_hsphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .exit = qcom_snps_hsphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .set_mode = qcom_snps_hsphy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const struct of_device_id qcom_snps_hsphy_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .compatible = "qcom,sm8150-usb-hs-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { .compatible = "qcom,usb-snps-hs-7nm-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { .compatible = "qcom,usb-snps-femto-v2-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) qcom_snps_hsphy_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int qcom_snps_hsphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct qcom_snps_hsphy *hsphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!hsphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) hsphy->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (IS_ERR(hsphy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return PTR_ERR(hsphy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) hsphy->ref_clk = devm_clk_get(dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (IS_ERR(hsphy->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = PTR_ERR(hsphy->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(dev, "failed to get ref clk, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (IS_ERR(hsphy->phy_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(dev, "failed to get phy core reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return PTR_ERR(hsphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) num = ARRAY_SIZE(hsphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = devm_regulator_bulk_get(dev, num, hsphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(dev, "failed to get regulator supplies: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * Prevent runtime pm from being ON by default. Users can enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * it using power/control in sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pm_runtime_forbid(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(dev, "failed to create phy, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hsphy->phy = generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_set_drvdata(dev, hsphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) phy_set_drvdata(generic_phy, hsphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (!IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_dbg(dev, "Registered Qcom-SNPS HS phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct platform_driver qcom_snps_hsphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .probe = qcom_snps_hsphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "qcom-snps-hs-femto-v2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .pm = &qcom_snps_hsphy_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .of_match_table = qcom_snps_hsphy_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) module_platform_driver(qcom_snps_hsphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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