Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef QCOM_PHY_QMP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define QCOM_PHY_QMP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* Only for QMP V2 PHY - QSERDES COM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define QSERDES_COM_BG_TIMER				0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define QSERDES_COM_SSC_EN_CENTER			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define QSERDES_COM_SSC_ADJ_PER1			0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define QSERDES_COM_SSC_ADJ_PER2			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define QSERDES_COM_SSC_PER1				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define QSERDES_COM_SSC_PER2				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define QSERDES_COM_SSC_STEP_SIZE1			0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define QSERDES_COM_SSC_STEP_SIZE2			0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN			0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define QSERDES_COM_CLK_ENABLE1				0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define QSERDES_COM_SYS_CLK_CTRL			0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define QSERDES_COM_SYSCLK_BUF_ENABLE			0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define QSERDES_COM_PLL_IVCO				0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define QSERDES_COM_LOCK_CMP1_MODE0			0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define QSERDES_COM_LOCK_CMP2_MODE0			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define QSERDES_COM_LOCK_CMP3_MODE0			0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define QSERDES_COM_LOCK_CMP1_MODE1			0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define QSERDES_COM_LOCK_CMP2_MODE1			0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define QSERDES_COM_LOCK_CMP3_MODE1			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define QSERDES_COM_BG_TRIM				0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define QSERDES_COM_CLK_EP_DIV				0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define QSERDES_COM_CP_CTRL_MODE0			0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define QSERDES_COM_CP_CTRL_MODE1			0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define QSERDES_COM_PLL_RCTRL_MODE0			0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define QSERDES_COM_PLL_RCTRL_MODE1			0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define QSERDES_COM_PLL_CCTRL_MODE0			0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define QSERDES_COM_PLL_CCTRL_MODE1			0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM			0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define QSERDES_COM_SYSCLK_EN_SEL			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define QSERDES_COM_RESETSM_CNTRL			0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define QSERDES_COM_RESTRIM_CTRL			0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define QSERDES_COM_RESCODE_DIV_NUM			0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define QSERDES_COM_LOCK_CMP_EN				0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define QSERDES_COM_LOCK_CMP_CFG			0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define QSERDES_COM_DEC_START_MODE0			0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define QSERDES_COM_DEC_START_MODE1			0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define QSERDES_COM_DIV_FRAC_START1_MODE0		0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define QSERDES_COM_DIV_FRAC_START2_MODE0		0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define QSERDES_COM_DIV_FRAC_START3_MODE0		0x0e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define QSERDES_COM_DIV_FRAC_START1_MODE1		0x0e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define QSERDES_COM_DIV_FRAC_START2_MODE1		0x0ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define QSERDES_COM_DIV_FRAC_START3_MODE1		0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1		0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define QSERDES_COM_VCO_TUNE_CTRL			0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define QSERDES_COM_VCO_TUNE_MAP			0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define QSERDES_COM_VCO_TUNE1_MODE0			0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define QSERDES_COM_VCO_TUNE2_MODE0			0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define QSERDES_COM_VCO_TUNE1_MODE1			0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define QSERDES_COM_VCO_TUNE2_MODE1			0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define QSERDES_COM_VCO_TUNE_TIMER1			0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define QSERDES_COM_VCO_TUNE_TIMER2			0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define QSERDES_COM_BG_CTRL				0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define QSERDES_COM_CLK_SELECT				0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define QSERDES_COM_HSCLK_SEL				0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define QSERDES_COM_CORECLK_DIV				0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define QSERDES_COM_CORE_CLK_EN				0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define QSERDES_COM_C_READY_STATUS			0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define QSERDES_COM_CMN_CONFIG				0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define QSERDES_COM_SVS_MODE_CLK_SEL			0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define QSERDES_COM_DEBUG_BUS0				0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define QSERDES_COM_DEBUG_BUS1				0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define QSERDES_COM_DEBUG_BUS2				0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define QSERDES_COM_DEBUG_BUS3				0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define QSERDES_COM_DEBUG_BUS_SEL			0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define QSERDES_COM_CORECLK_DIV_MODE1			0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* Only for QMP V2 PHY - TX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define QSERDES_TX_EMP_POST1_LVL			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define QSERDES_TX_SLEW_CNTL				0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define QSERDES_TX_RES_CODE_LANE_OFFSET			0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define QSERDES_TX_DEBUG_BUS_SEL			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN	0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define QSERDES_TX_LANE_MODE				0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define QSERDES_TX_RCV_DETECT_LVL_2			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* Only for QMP V2 PHY - RX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define QSERDES_RX_UCDR_SO_GAIN_HALF			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define QSERDES_RX_UCDR_SO_GAIN				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE	0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define QSERDES_RX_RX_TERM_BW				0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define QSERDES_RX_RX_EQ_GAIN1_LSB			0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define QSERDES_RX_RX_EQ_GAIN1_MSB			0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define QSERDES_RX_RX_EQ_GAIN2_LSB			0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define QSERDES_RX_RX_EQ_GAIN2_MSB			0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2		0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3		0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4		0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QSERDES_RX_SIGDET_ENABLES			0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QSERDES_RX_SIGDET_CNTRL				0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QSERDES_RX_SIGDET_LVL				0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL		0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QSERDES_RX_RX_BAND				0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QSERDES_RX_RX_INTERFACE_MODE			0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Only for QMP V2 PHY - PCS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QPHY_POWER_DOWN_CONTROL				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QPHY_TXDEEMPH_M6DB_V0				0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QPHY_TXDEEMPH_M3P5DB_V0				0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QPHY_ENDPOINT_REFCLK_DRIVE			0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QPHY_RX_IDLE_DTCT_CNTRL				0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QPHY_POWER_STATE_CONFIG1			0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QPHY_POWER_STATE_CONFIG2			0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QPHY_POWER_STATE_CONFIG4			0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QPHY_LOCK_DETECT_CONFIG1			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QPHY_LOCK_DETECT_CONFIG2			0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QPHY_LOCK_DETECT_CONFIG3			0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK			0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB		0x1A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QPHY_OSC_DTCT_ACTIONS				0x1AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QPHY_RX_SIGDET_LVL				0x1D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB		0x1DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB		0x1E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Only for QMP V3 & V4 PHY - DP COM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QPHY_V3_DP_COM_SW_RESET				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QPHY_V3_DP_COM_POWER_DOWN_CTRL			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QPHY_V3_DP_COM_SWI_CTRL				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define QPHY_V3_DP_COM_TYPEC_CTRL			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QPHY_V3_DP_COM_RESET_OVRD_CTRL			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Only for QMP V3 PHY - QSERDES COM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QSERDES_V3_COM_ATB_SEL1				0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define QSERDES_V3_COM_ATB_SEL2				0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QSERDES_V3_COM_FREQ_UPDATE			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QSERDES_V3_COM_BG_TIMER				0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QSERDES_V3_COM_SSC_EN_CENTER			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QSERDES_V3_COM_SSC_ADJ_PER1			0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QSERDES_V3_COM_SSC_ADJ_PER2			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QSERDES_V3_COM_SSC_PER1				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QSERDES_V3_COM_SSC_PER2				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QSERDES_V3_COM_SSC_STEP_SIZE1			0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QSERDES_V3_COM_SSC_STEP_SIZE2			0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN		0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define QSERDES_V3_COM_BIAS_EN				0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define QSERDES_V3_COM_BIAS_EN_MUX			0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define QSERDES_V3_COM_CLKBUF_R_EN			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define QSERDES_V3_COM_CLKBUF_L_EN			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QSERDES_V3_COM_CLK_ENABLE1			0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QSERDES_V3_COM_SYS_CLK_CTRL			0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QSERDES_V3_COM_PLL_IVCO				0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define QSERDES_V3_COM_LOCK_CMP1_MODE0			0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QSERDES_V3_COM_LOCK_CMP2_MODE0			0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define QSERDES_V3_COM_LOCK_CMP3_MODE0			0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define QSERDES_V3_COM_LOCK_CMP1_MODE1			0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define QSERDES_V3_COM_LOCK_CMP2_MODE1			0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QSERDES_V3_COM_LOCK_CMP3_MODE1			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define QSERDES_V3_COM_CLK_EP_DIV			0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define QSERDES_V3_COM_CP_CTRL_MODE0			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define QSERDES_V3_COM_CP_CTRL_MODE1			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QSERDES_V3_COM_PLL_RCTRL_MODE0			0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QSERDES_V3_COM_PLL_RCTRL_MODE1			0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QSERDES_V3_COM_PLL_CCTRL_MODE0			0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QSERDES_V3_COM_PLL_CCTRL_MODE1			0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QSERDES_V3_COM_SYSCLK_EN_SEL			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QSERDES_V3_COM_RESETSM_CNTRL			0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QSERDES_V3_COM_RESETSM_CNTRL2			0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QSERDES_V3_COM_LOCK_CMP_EN			0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QSERDES_V3_COM_LOCK_CMP_CFG			0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QSERDES_V3_COM_DEC_START_MODE0			0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define QSERDES_V3_COM_DEC_START_MODE1			0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0		0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0		0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0		0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1		0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1		0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1		0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define QSERDES_V3_COM_INTEGLOOP_INITVAL		0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0		0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0		0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1		0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1		0x0e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QSERDES_V3_COM_VCO_TUNE_CTRL			0x0ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define QSERDES_V3_COM_VCO_TUNE_MAP			0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define QSERDES_V3_COM_VCO_TUNE1_MODE0			0x0f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QSERDES_V3_COM_VCO_TUNE2_MODE0			0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define QSERDES_V3_COM_VCO_TUNE1_MODE1			0x0fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define QSERDES_V3_COM_VCO_TUNE2_MODE1			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define QSERDES_V3_COM_VCO_TUNE_INITVAL1		0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define QSERDES_V3_COM_VCO_TUNE_INITVAL2		0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define QSERDES_V3_COM_VCO_TUNE_TIMER1			0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define QSERDES_V3_COM_VCO_TUNE_TIMER2			0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define QSERDES_V3_COM_CLK_SELECT			0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define QSERDES_V3_COM_HSCLK_SEL			0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define QSERDES_V3_COM_CORECLK_DIV_MODE0		0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define QSERDES_V3_COM_CORECLK_DIV_MODE1		0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define QSERDES_V3_COM_CORE_CLK_EN			0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define QSERDES_V3_COM_C_READY_STATUS			0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define QSERDES_V3_COM_CMN_CONFIG			0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define QSERDES_V3_COM_SVS_MODE_CLK_SEL			0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define QSERDES_V3_COM_DEBUG_BUS0			0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define QSERDES_V3_COM_DEBUG_BUS1			0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define QSERDES_V3_COM_DEBUG_BUS2			0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define QSERDES_V3_COM_DEBUG_BUS3			0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define QSERDES_V3_COM_DEBUG_BUS_SEL			0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define QSERDES_V3_COM_CMN_MODE				0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Only for QMP V3 PHY - TX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define QSERDES_V3_TX_BIST_MODE_LANENO			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define QSERDES_V3_TX_CLKBUF_ENABLE			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define QSERDES_V3_TX_TX_EMP_POST1_LVL			0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define QSERDES_V3_TX_TX_DRV_LVL			0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) # define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define QSERDES_V3_TX_RESET_TSYNC_EN			0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN		0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define QSERDES_V3_TX_TX_BAND				0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define QSERDES_V3_TX_SLEW_CNTL				0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define QSERDES_V3_TX_INTERFACE_SELECT			0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define QSERDES_V3_TX_RES_CODE_LANE_TX			0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define QSERDES_V3_TX_RES_CODE_LANE_RX			0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX		0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX		0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define QSERDES_V3_TX_DEBUG_BUS_SEL			0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN		0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define QSERDES_V3_TX_HIGHZ_DRVR_EN			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define QSERDES_V3_TX_TX_POL_INV			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN	0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define QSERDES_V3_TX_LANE_MODE_1			0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define QSERDES_V3_TX_RCV_DETECT_LVL_2			0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN			0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define QSERDES_V3_TX_TX_INTERFACE_MODE			0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define QSERDES_V3_TX_VMODE_CTRL1			0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Only for QMP V3 PHY - RX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define QSERDES_V3_RX_UCDR_FO_GAIN			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF			0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define QSERDES_V3_RX_UCDR_SO_GAIN			0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF		0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER		0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN			0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define QSERDES_V3_RX_UCDR_PI_CONTROLS			0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define QSERDES_V3_RX_RX_TERM_BW			0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define QSERDES_V3_RX_VGA_CAL_CNTRL2			0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB			0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB			0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2		0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3		0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4		0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x0fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define QSERDES_V3_RX_SIGDET_ENABLES			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define QSERDES_V3_RX_SIGDET_CNTRL			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define QSERDES_V3_RX_SIGDET_LVL			0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL		0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define QSERDES_V3_RX_RX_BAND				0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define QSERDES_V3_RX_RX_MODE_00			0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define QSERDES_V3_RX_RX_MODE_01			0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Only for QMP V3 PHY - PCS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define QPHY_V3_PCS_TXMGN_V0				0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define QPHY_V3_PCS_TXMGN_V1				0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define QPHY_V3_PCS_TXMGN_V2				0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define QPHY_V3_PCS_TXMGN_V3				0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define QPHY_V3_PCS_TXMGN_V4				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define QPHY_V3_PCS_TXMGN_LS				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL		0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL		0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0			0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0			0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1			0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1			0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2			0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2			0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3			0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3			0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4			0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4			0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS			0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE		0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL			0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define QPHY_V3_PCS_RATE_SLEW_CNTRL			0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define QPHY_V3_PCS_POWER_STATE_CONFIG1			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define QPHY_V3_PCS_POWER_STATE_CONFIG2			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define QPHY_V3_PCS_POWER_STATE_CONFIG4			0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L		0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H		0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L			0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H			0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2			0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3			0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define QPHY_V3_PCS_TSYNC_RSYNC_TIME			0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK		0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME		0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK		0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME		0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME		0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define QPHY_V3_PCS_FLL_CNTRL1				0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define QPHY_V3_PCS_FLL_CNTRL2				0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define QPHY_V3_PCS_FLL_CNT_VAL_L			0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL			0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define QPHY_V3_PCS_FLL_MAN_CODE			0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL			0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME			0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define QPHY_V3_PCS_RX_SIGDET_CTRL1			0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define QPHY_V3_PCS_RX_SIGDET_CTRL2			0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define QPHY_V3_PCS_OSC_DTCT_ACTIONS			0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define QPHY_V3_PCS_SIGDET_CNTRL			0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define QPHY_V3_PCS_TX_MID_TERM_CTRL1			0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define QPHY_V3_PCS_MULTI_LANE_CTRL1			0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define QPHY_V3_PCS_RX_SIGDET_LVL			0x1d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB	0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB	0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1			0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2			0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Only for QMP V3 PHY - PCS_MISC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define QPHY_V3_PCS_MISC_CLAMP_ENABLE			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4		0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Only for QMP V3 PHY - DP PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define QSERDES_V3_DP_PHY_REVISION_ID0			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define QSERDES_V3_DP_PHY_REVISION_ID1			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define QSERDES_V3_DP_PHY_REVISION_ID2			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define QSERDES_V3_DP_PHY_REVISION_ID3			0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define QSERDES_V3_DP_PHY_CFG				0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define QSERDES_V3_DP_PHY_PD_CTL			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) # define DP_PHY_PD_CTL_PWRDN				0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) # define DP_PHY_PD_CTL_PSR_PWRDN			0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) # define DP_PHY_PD_CTL_AUX_PWRDN			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) # define DP_PHY_PD_CTL_LANE_0_1_PWRDN			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) # define DP_PHY_PD_CTL_LANE_2_3_PWRDN			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) # define DP_PHY_PD_CTL_PLL_PWRDN			0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) # define DP_PHY_PD_CTL_DP_CLAMP_EN			0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define QSERDES_V3_DP_PHY_MODE				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define QSERDES_V3_DP_PHY_AUX_CFG0			0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define QSERDES_V3_DP_PHY_AUX_CFG1			0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define QSERDES_V3_DP_PHY_AUX_CFG2			0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define QSERDES_V3_DP_PHY_AUX_CFG3			0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define QSERDES_V3_DP_PHY_AUX_CFG4			0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define QSERDES_V3_DP_PHY_AUX_CFG5			0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define QSERDES_V3_DP_PHY_AUX_CFG6			0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define QSERDES_V3_DP_PHY_AUX_CFG7			0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define QSERDES_V3_DP_PHY_AUX_CFG8			0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define QSERDES_V3_DP_PHY_AUX_CFG9			0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK		0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) # define PHY_AUX_STOP_ERR_MASK				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) # define PHY_AUX_DEC_ERR_MASK				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) # define PHY_AUX_SYNC_ERR_MASK				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) # define PHY_AUX_ALIGN_ERR_MASK				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) # define PHY_AUX_REQ_ERR_MASK				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR		0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define QSERDES_V3_DP_PHY_AUX_BIST_CFG			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define QSERDES_V3_DP_PHY_VCO_DIV			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL		0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL		0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define QSERDES_V3_DP_PHY_SPARE0			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define DP_PHY_SPARE0_MASK				0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT		0x04(0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define QSERDES_V3_DP_PHY_STATUS			0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Only for QMP V4 PHY - QSERDES COM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define QSERDES_V4_COM_SSC_EN_CENTER			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define QSERDES_V4_COM_SSC_PER1				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define QSERDES_V4_COM_SSC_PER2				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0		0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0		0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1		0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1		0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE		0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define QSERDES_V4_COM_PLL_IVCO				0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define QSERDES_V4_COM_CMN_IPTRIM			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define QSERDES_V4_COM_CP_CTRL_MODE0			0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define QSERDES_V4_COM_CP_CTRL_MODE1			0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define QSERDES_V4_COM_PLL_RCTRL_MODE0			0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define QSERDES_V4_COM_PLL_RCTRL_MODE1			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define QSERDES_V4_COM_PLL_CCTRL_MODE0			0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define QSERDES_V4_COM_PLL_CCTRL_MODE1			0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define QSERDES_V4_COM_SYSCLK_EN_SEL			0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define QSERDES_V4_COM_LOCK_CMP_EN			0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define QSERDES_V4_COM_LOCK_CMP1_MODE0			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define QSERDES_V4_COM_LOCK_CMP2_MODE0			0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define QSERDES_V4_COM_LOCK_CMP1_MODE1			0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define QSERDES_V4_COM_DEC_START_MODE0			0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define QSERDES_V4_COM_LOCK_CMP2_MODE1			0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define QSERDES_V4_COM_DEC_START_MODE1			0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0		0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0		0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0		0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1		0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1		0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1		0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define QSERDES_V4_COM_VCO_TUNE_MAP			0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define QSERDES_V4_COM_VCO_TUNE1_MODE0			0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define QSERDES_V4_COM_VCO_TUNE2_MODE0			0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define QSERDES_V4_COM_VCO_TUNE1_MODE1			0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define QSERDES_V4_COM_VCO_TUNE2_MODE1			0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define QSERDES_V4_COM_VCO_TUNE_INITVAL2		0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define QSERDES_V4_COM_HSCLK_SEL			0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL		0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define QSERDES_V4_COM_CORECLK_DIV_MODE1		0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define QSERDES_V4_COM_SVS_MODE_CLK_SEL			0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x1b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL		0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Only for QMP V4 PHY - TX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define QSERDES_V4_TX_RES_CODE_LANE_TX			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define QSERDES_V4_TX_RES_CODE_LANE_RX			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define QSERDES_V4_TX_LANE_MODE_1			0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define QSERDES_V4_TX_LANE_MODE_2			0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define QSERDES_V4_TX_RCV_DETECT_LVL_2			0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1	0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1	0xdC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1	0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1	0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN			0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define QSERDES_V4_TX_PI_QEC_CTRL		0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Only for QMP V4 PHY - RX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define QSERDES_V4_RX_UCDR_FO_GAIN			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define QSERDES_V4_RX_UCDR_SO_GAIN			0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN		0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW		0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH		0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define QSERDES_V4_RX_UCDR_PI_CONTROLS			0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define QSERDES_V4_RX_UCDR_PI_CTRL2			0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define QSERDES_V4_RX_UCDR_SB2_THRESH1			0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define QSERDES_V4_RX_UCDR_SB2_THRESH2			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define QSERDES_V4_RX_UCDR_SB2_GAIN1			0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define QSERDES_V4_RX_UCDR_SB2_GAIN2			0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define QSERDES_V4_RX_AC_JTAG_ENABLE			0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define QSERDES_V4_RX_AC_JTAG_MODE			0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define QSERDES_V4_RX_RX_TERM_BW			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define QSERDES_V4_RX_VGA_CAL_CNTRL1			0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define QSERDES_V4_RX_VGA_CAL_CNTRL2			0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define QSERDES_V4_RX_GM_CAL				0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2		0x0ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3		0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4		0x0f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW		0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH		0x0fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1	0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2		0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define QSERDES_V4_RX_SIGDET_CNTRL			0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define QSERDES_V4_RX_SIGDET_LVL			0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL		0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define QSERDES_V4_RX_RX_BAND				0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define QSERDES_V4_RX_RX_MODE_00_LOW			0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define QSERDES_V4_RX_RX_MODE_00_HIGH			0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define QSERDES_V4_RX_RX_MODE_00_HIGH2			0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define QSERDES_V4_RX_RX_MODE_00_HIGH3			0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define QSERDES_V4_RX_RX_MODE_00_HIGH4			0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define QSERDES_V4_RX_RX_MODE_01_LOW			0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define QSERDES_V4_RX_RX_MODE_01_HIGH			0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define QSERDES_V4_RX_RX_MODE_01_HIGH2			0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define QSERDES_V4_RX_RX_MODE_01_HIGH3			0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define QSERDES_V4_RX_RX_MODE_01_HIGH4			0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define QSERDES_V4_RX_RX_MODE_10_LOW			0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define QSERDES_V4_RX_RX_MODE_10_HIGH			0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define QSERDES_V4_RX_RX_MODE_10_HIGH2			0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define QSERDES_V4_RX_RX_MODE_10_HIGH3			0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define QSERDES_V4_RX_RX_MODE_10_HIGH4			0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define QSERDES_V4_RX_DFE_EN_TIMER			0x1b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET		0x1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define QSERDES_V4_RX_DCC_CTRL1				0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define QSERDES_V4_RX_VTH_CODE				0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Only for QMP V4 PHY - UFS PCS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define QPHY_V4_PCS_UFS_PHY_START				0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define QPHY_V4_PCS_UFS_SW_RESET				0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB		0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB		0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define QPHY_V4_PCS_UFS_PLL_CNTL				0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL			0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL			0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY			0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY			0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL			0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define QPHY_V4_PCS_UFS_LINECFG_DISABLE				0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME			0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2				0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND			0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND				0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define QPHY_V4_PCS_UFS_READY_STATUS			0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1			0x1d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1			0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* PCIE GEN3 COM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define PCIE_GEN3_QHP_COM_SSC_PER1			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define PCIE_GEN3_QHP_COM_SSC_PER2			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define PCIE_GEN3_QHP_COM_CLK_ENABLE1			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0		0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1		0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define PCIE_GEN3_QHP_COM_BGV_TRIM			0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0			0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1			0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1		0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0		0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL			0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2			0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN			0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define PCIE_GEN3_QHP_COM_DEC_START_MODE0		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define PCIE_GEN3_QHP_COM_DEC_START_MODE1		0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0		0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0		0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0		0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1		0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1		0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1		0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0		0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1		0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP			0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define PCIE_GEN3_QHP_COM_BG_CTRL			0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define PCIE_GEN3_QHP_COM_CLK_SELECT			0x1cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define PCIE_GEN3_QHP_COM_HSCLK_SEL1			0x1d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define PCIE_GEN3_QHP_COM_CORECLK_DIV			0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define PCIE_GEN3_QHP_COM_CORE_CLK_EN			0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define PCIE_GEN3_QHP_COM_CMN_CONFIG			0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL		0x1fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1		0x21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define PCIE_GEN3_QHP_COM_CMN_MODE			0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1			0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2			0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* PCIE GEN3 QHP Lane registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define PCIE_GEN3_QHP_L0_DRVR_CTRL0			0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define PCIE_GEN3_QHP_L0_DRVR_CTRL1			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define PCIE_GEN3_QHP_L0_DRVR_CTRL2			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PCIE_GEN3_QHP_L0_TX_BAND_MODE			0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define PCIE_GEN3_QHP_L0_LANE_MODE			0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define PCIE_GEN3_QHP_L0_PARALLEL_RATE			0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0			0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1			0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2			0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2		0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0		0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1		0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2		0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE		0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define PCIE_GEN3_QHP_L0_RXENGINE_EN0			0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME		0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME		0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME		0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME		0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define PCIE_GEN3_QHP_L0_VGA_GAIN			0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define PCIE_GEN3_QHP_L0_DFE_GAIN			0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define PCIE_GEN3_QHP_L0_EQ_GAIN			0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define PCIE_GEN3_QHP_L0_OFFSET_GAIN			0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define PCIE_GEN3_QHP_L0_PRE_GAIN			0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define PCIE_GEN3_QHP_L0_VGA_INITVAL			0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define PCIE_GEN3_QHP_L0_EQ_INTVAL			0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define PCIE_GEN3_QHP_L0_EDAC_INITVAL			0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define PCIE_GEN3_QHP_L0_RXEQ_INITB0			0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define PCIE_GEN3_QHP_L0_RXEQ_INITB1			0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1		0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define PCIE_GEN3_QHP_L0_RXEQ_CTRL			0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0		0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1		0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2		0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0		0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1		0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2		0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG			0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define PCIE_GEN3_QHP_L0_RX_BAND			0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0		0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1		0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2		0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES			0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL			0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL		0x238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define PCIE_GEN3_QHP_L0_DCC_GAIN			0x2a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define PCIE_GEN3_QHP_L0_RSM_START			0x2a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL			0x2ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL			0x2b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0			0x2b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define PCIE_GEN3_QHP_L0_TS0_TIMER			0x2c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE		0x2c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET		0x2cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* PCIE GEN3 PCS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG		0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5		0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG		0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Only for QMP V4 PHY - USB/PCIe PCS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define QPHY_V4_PCS_SW_RESET				0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define QPHY_V4_PCS_REVISION_ID0			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define QPHY_V4_PCS_REVISION_ID1			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define QPHY_V4_PCS_REVISION_ID2			0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define QPHY_V4_PCS_REVISION_ID3			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define QPHY_V4_PCS_PCS_STATUS1				0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define QPHY_V4_PCS_PCS_STATUS2				0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define QPHY_V4_PCS_PCS_STATUS3				0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define QPHY_V4_PCS_PCS_STATUS4				0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define QPHY_V4_PCS_PCS_STATUS5				0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define QPHY_V4_PCS_PCS_STATUS6				0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define QPHY_V4_PCS_PCS_STATUS7				0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS			0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS			0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS			0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS			0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define QPHY_V4_PCS_POWER_DOWN_CONTROL			0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define QPHY_V4_PCS_START_CONTROL			0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define QPHY_V4_PCS_INSIG_SW_CTRL1			0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define QPHY_V4_PCS_INSIG_SW_CTRL2			0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define QPHY_V4_PCS_INSIG_SW_CTRL3			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define QPHY_V4_PCS_INSIG_SW_CTRL4			0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define QPHY_V4_PCS_INSIG_SW_CTRL5			0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define QPHY_V4_PCS_INSIG_SW_CTRL6			0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define QPHY_V4_PCS_INSIG_SW_CTRL7			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define QPHY_V4_PCS_INSIG_SW_CTRL8			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define QPHY_V4_PCS_INSIG_MX_CTRL1			0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define QPHY_V4_PCS_INSIG_MX_CTRL2			0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define QPHY_V4_PCS_INSIG_MX_CTRL3			0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define QPHY_V4_PCS_INSIG_MX_CTRL4			0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define QPHY_V4_PCS_INSIG_MX_CTRL5			0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define QPHY_V4_PCS_INSIG_MX_CTRL7			0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define QPHY_V4_PCS_INSIG_MX_CTRL8			0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define QPHY_V4_PCS_OUTSIG_SW_CTRL1			0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define QPHY_V4_PCS_OUTSIG_MX_CTRL1			0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define QPHY_V4_PCS_CLAMP_ENABLE			0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define QPHY_V4_PCS_POWER_STATE_CONFIG1			0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define QPHY_V4_PCS_POWER_STATE_CONFIG2			0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define QPHY_V4_PCS_FLL_CNTRL1				0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define QPHY_V4_PCS_FLL_CNTRL2				0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define QPHY_V4_PCS_FLL_CNT_VAL_L			0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL			0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define QPHY_V4_PCS_FLL_MAN_CODE			0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define QPHY_V4_PCS_TEST_CONTROL1			0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define QPHY_V4_PCS_TEST_CONTROL2			0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define QPHY_V4_PCS_TEST_CONTROL3			0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define QPHY_V4_PCS_TEST_CONTROL4			0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define QPHY_V4_PCS_TEST_CONTROL5			0x0bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define QPHY_V4_PCS_TEST_CONTROL6			0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1			0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2			0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3			0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4			0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5			0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6			0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1			0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2			0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3			0x0e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define QPHY_V4_PCS_BIST_CTRL				0x0e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define QPHY_V4_PCS_PRBS_POLY0				0x0ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define QPHY_V4_PCS_PRBS_POLY1				0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define QPHY_V4_PCS_FIXED_PAT0				0x0f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define QPHY_V4_PCS_FIXED_PAT1				0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define QPHY_V4_PCS_FIXED_PAT2				0x0fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define QPHY_V4_PCS_FIXED_PAT3				0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define QPHY_V4_PCS_FIXED_PAT4				0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define QPHY_V4_PCS_FIXED_PAT5				0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define QPHY_V4_PCS_FIXED_PAT6				0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define QPHY_V4_PCS_FIXED_PAT7				0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define QPHY_V4_PCS_FIXED_PAT8				0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define QPHY_V4_PCS_FIXED_PAT9				0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define QPHY_V4_PCS_FIXED_PAT10				0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define QPHY_V4_PCS_FIXED_PAT11				0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define QPHY_V4_PCS_FIXED_PAT12				0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define QPHY_V4_PCS_FIXED_PAT13				0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define QPHY_V4_PCS_FIXED_PAT14				0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define QPHY_V4_PCS_FIXED_PAT15				0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define QPHY_V4_PCS_TXMGN_CONFIG			0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define QPHY_V4_PCS_G12S1_TXMGN_V0			0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define QPHY_V4_PCS_G12S1_TXMGN_V1			0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define QPHY_V4_PCS_G12S1_TXMGN_V2			0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define QPHY_V4_PCS_G12S1_TXMGN_V3			0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define QPHY_V4_PCS_G12S1_TXMGN_V4			0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS			0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS			0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS			0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS			0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS			0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define QPHY_V4_PCS_G3S2_TXMGN_MAIN			0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS			0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB			0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB		0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define QPHY_V4_PCS_G3S2_PRE_GAIN			0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define QPHY_V4_PCS_G3S2_POST_GAIN			0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET		0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS			0x17c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define QPHY_V4_PCS_G3S2_POST_GAIN_RS			0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS		0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define QPHY_V4_PCS_RX_SIGDET_LVL			0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL		0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L		0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H		0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define QPHY_V4_PCS_RATE_SLEW_CNTRL1			0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define QPHY_V4_PCS_RATE_SLEW_CNTRL2			0x19c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK		0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L	0x1a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H	0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define QPHY_V4_PCS_TSYNC_RSYNC_TIME			0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define QPHY_V4_PCS_CDR_RESET_TIME			0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define QPHY_V4_PCS_TSYNC_DLY_TIME			0x1b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define QPHY_V4_PCS_ELECIDLE_DLY_SEL			0x1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define QPHY_V4_PCS_CMN_ACK_OUT_SEL			0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1		0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2		0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3		0x1c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4		0x1cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define QPHY_V4_PCS_PCS_TX_RX_CONFIG			0x1d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL			0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG			0x1d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define QPHY_V4_PCS_EQ_CONFIG1				0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define QPHY_V4_PCS_EQ_CONFIG2				0x1e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define QPHY_V4_PCS_EQ_CONFIG3				0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define QPHY_V4_PCS_EQ_CONFIG4				0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define QPHY_V4_PCS_EQ_CONFIG5				0x1ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS		0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL		0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2		0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS	0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR		0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART		0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL		0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START	0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME		0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME		0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME		0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2	0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L		0x33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H		0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD		0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY		0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH		0x34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL		0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL	0x354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define QPHY_V4_PCS_USB3_TEST_CONTROL			0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL	0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2	0x638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Only for QMP V4 PHY - PCS_MISC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define QPHY_V4_PCS_MISC_TYPEC_CTRL			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define QPHY_V4_PCS_MISC_CLAMP_ENABLE			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #endif