^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "phy-qcom-qmp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* QPHY_SW_RESET bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SW_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* QPHY_POWER_DOWN_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SW_PWRDN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REFCLK_DRV_DSBL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* QPHY_START_CONTROL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SERDES_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCS_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLL_READY_GATE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* QPHY_PCS_STATUS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHYSTATUS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCS_READY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* DP PHY soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SW_DPPHY_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SW_DPPHY_RESET_MUX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* USB3 PHY soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SW_USB3PHY_RESET BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SW_USB3PHY_RESET_MUX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB3_MODE BIT(0) /* enables USB3 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DP_MODE BIT(1) /* enables DP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ARCVR_DTCT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ALFPS_DTCT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ARCVR_DTCT_EVENT_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IRQ_CLEAR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RCVR_DETECT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLAMP_EN BIT(0) /* enables i/o clamp_n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_INIT_COMPLETE_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define POWER_DOWN_DELAY_US_MIN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define POWER_DOWN_DELAY_US_MAX 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX_PROP_NAME 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Define the assumed distance between lanes for underspecified device trees. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QMP_PHY_LEGACY_LANE_STRIDE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct qmp_phy_init_tbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * register part of layout ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * if yes, then offset gives index in the reg-layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool in_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * mask of lanes for which this register is written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * for cases when second lane needs different values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 lane_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QMP_PHY_INIT_CFG(o, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .val = v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .lane_mask = 0xff, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QMP_PHY_INIT_CFG_L(o, v) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .val = v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .in_layout = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .lane_mask = 0xff, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QMP_PHY_INIT_CFG_LANE(o, v, l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .val = v, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .lane_mask = l, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* set of registers with offsets different per-PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum qphy_reg_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Common block control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) QPHY_COM_SW_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) QPHY_COM_POWER_DOWN_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) QPHY_COM_START_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) QPHY_COM_PCS_READY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* PCS registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) QPHY_PLL_LOCK_CHK_DLY_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) QPHY_FLL_CNTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) QPHY_FLL_CNTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) QPHY_FLL_CNT_VAL_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) QPHY_FLL_CNT_VAL_H_TOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) QPHY_FLL_MAN_CODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) QPHY_SW_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) QPHY_START_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) QPHY_PCS_READY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) QPHY_PCS_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) QPHY_PCS_AUTONOMOUS_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) QPHY_PCS_POWER_DOWN_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Keep last to ensure regs_layout arrays are properly initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) QPHY_LAYOUT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [QPHY_START_CTRL] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [QPHY_PCS_READY_STATUS] = 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [QPHY_COM_SW_RESET] = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [QPHY_COM_START_CONTROL] = 0x408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [QPHY_COM_PCS_READY_STATUS] = 0x448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [QPHY_FLL_CNTRL1] = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [QPHY_FLL_CNTRL2] = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [QPHY_FLL_CNT_VAL_L] = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [QPHY_FLL_MAN_CODE] = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [QPHY_START_CTRL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [QPHY_PCS_STATUS] = 0x174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [QPHY_FLL_CNTRL1] = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [QPHY_FLL_CNTRL2] = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [QPHY_FLL_CNT_VAL_L] = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [QPHY_FLL_MAN_CODE] = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [QPHY_START_CTRL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [QPHY_PCS_STATUS] = 0x17c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [QPHY_START_CTRL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) [QPHY_PCS_STATUS] = 0x174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [QPHY_START_CTRL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [QPHY_PCS_STATUS] = 0x174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [QPHY_START_CTRL] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [QPHY_PCS_STATUS] = 0x2ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [QPHY_START_CTRL] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [QPHY_PCS_STATUS] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [QPHY_SW_RESET] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [QPHY_START_CTRL] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [QPHY_PCS_STATUS] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x614,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [QPHY_START_CTRL] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [QPHY_PCS_READY_STATUS] = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* PLL and Loop filter settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* SSC settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* PLL and Loop filter settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* SSC settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* FLL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Lock Det settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* FLL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Lock Det settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* FLL settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Lock Det settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* Rate B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* Rate B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* Lock Det settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* struct qmp_phy_cfg - per-PHY initialization config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) struct qmp_phy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* phy-type - PCIE/UFS/USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* number of lanes provided by phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) const struct qmp_phy_init_tbl *serdes_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) int serdes_tbl_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) const struct qmp_phy_init_tbl *tx_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) int tx_tbl_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) const struct qmp_phy_init_tbl *rx_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) int rx_tbl_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) const struct qmp_phy_init_tbl *pcs_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) int pcs_tbl_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) const struct qmp_phy_init_tbl *pcs_misc_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) int pcs_misc_tbl_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /* Init sequence for DP PHY block link rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) const struct qmp_phy_init_tbl *serdes_tbl_rbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) int serdes_tbl_rbr_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) const struct qmp_phy_init_tbl *serdes_tbl_hbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) int serdes_tbl_hbr_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) int serdes_tbl_hbr2_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) int serdes_tbl_hbr3_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* clock ids to be requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) const char * const *clk_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* resets to be requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) const char * const *reset_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) int num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* regulators to be requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) const char * const *vreg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) int num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* array of registers with different offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) const unsigned int *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) unsigned int start_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) unsigned int pwrdn_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) unsigned int mask_com_pcs_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /* true, if PHY has a separate PHY_COM control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) bool has_phy_com_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* true, if PHY has a reset for individual lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) bool has_lane_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* true, if PHY needs delay after POWER_DOWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) bool has_pwrdn_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* power_down delay in usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) int pwrdn_delay_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) int pwrdn_delay_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* true, if PHY has a separate DP_COM control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) bool has_phy_dp_com_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* true, if PHY has secondary tx/rx lanes to be configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) bool is_dual_lane_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* true, if PCS block has no separate SW_RESET register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) bool no_pcs_sw_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct qmp_phy_combo_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) const struct qmp_phy_cfg *usb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) const struct qmp_phy_cfg *dp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) * struct qmp_phy - per-lane phy descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) * @phy: generic phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * @cfg: phy specific configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) * @tx: iomapped memory space for lane's tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * @rx: iomapped memory space for lane's rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * @pcs: iomapped memory space for lane's pcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) * @pcs_misc: iomapped memory space for lane's pcs_misc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) * @pipe_clk: pipe lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) * @index: lane index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * @qmp: QMP phy to which this lane belongs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * @lane_rst: lane's reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * @mode: current PHY mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) struct qmp_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) const struct qmp_phy_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) void __iomem *serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) void __iomem *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) void __iomem *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) void __iomem *pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) void __iomem *tx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) void __iomem *rx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) void __iomem *pcs_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) struct clk *pipe_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct qcom_qmp *qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) struct reset_control *lane_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) enum phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) unsigned int dp_aux_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) struct phy_configure_opts_dp dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct qmp_phy_dp_clks *dp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct qmp_phy_dp_clks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) struct qmp_phy *qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) struct clk_hw dp_link_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) struct clk_hw dp_pixel_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * struct qcom_qmp - structure holding QMP phy block attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * @dev: device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * @dp_com: iomapped memory space for phy's dp_com control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) * @clks: array of clocks required by phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) * @resets: array of resets required by phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * @vregs: regulator supplies bulk data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * @phys: array of per-lane phy descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * @phy_mutex: mutex lock for PHY common block initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * @init_count: phy common block initialization count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * @ufs_reset: optional UFS PHY reset handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) struct qcom_qmp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) void __iomem *dp_com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) struct reset_control **resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct regulator_bulk_data *vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct qmp_phy **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) struct mutex phy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) int init_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct reset_control *ufs_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) reg = readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) reg |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) writel(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* ensure that above write is through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) reg = readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) reg &= ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) writel(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* ensure that above write is through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /* list of clocks required by phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static const char * const msm8996_phy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) "aux", "cfg_ahb", "ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static const char * const msm8996_ufs_phy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) "ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const char * const qmp_v3_phy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "aux", "cfg_ahb", "ref", "com_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static const char * const sdm845_pciephy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "aux", "cfg_ahb", "ref", "refgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static const char * const qmp_v4_phy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) "aux", "ref_clk_src", "ref", "com_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* the primary usb3 phy on sm8250 doesn't have a ref clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) "aux", "ref_clk_src", "com_aux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static const char * const sdm845_ufs_phy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) "ref", "ref_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* list of resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static const char * const msm8996_pciephy_reset_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) "phy", "common", "cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static const char * const msm8996_usb3phy_reset_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) "phy", "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static const char * const sc7180_usb3phy_reset_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) "phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static const char * const sdm845_pciephy_reset_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) "phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* list of regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static const char * const qmp_phy_vreg_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) "vdda-phy", "vdda-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .serdes_tbl = ipq8074_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .tx_tbl = msm8996_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .rx_tbl = ipq8074_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .pcs_tbl = ipq8074_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .clk_list = msm8996_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .regs = usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .type = PHY_TYPE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .nlanes = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .serdes_tbl = msm8996_pcie_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .tx_tbl = msm8996_pcie_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .rx_tbl = msm8996_pcie_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .pcs_tbl = msm8996_pcie_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .clk_list = msm8996_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .reset_list = msm8996_pciephy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .regs = pciephy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .start_ctrl = PCS_START | PLL_READY_GATE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .mask_com_pcs_ready = PCS_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .has_phy_com_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .has_lane_rst = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static const struct qmp_phy_cfg msm8996_ufs_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .type = PHY_TYPE_UFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .serdes_tbl = msm8996_ufs_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .tx_tbl = msm8996_ufs_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .rx_tbl = msm8996_ufs_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .clk_list = msm8996_ufs_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .regs = msm8996_ufsphy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .start_ctrl = SERDES_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .no_pcs_sw_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .serdes_tbl = msm8996_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .tx_tbl = msm8996_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .rx_tbl = msm8996_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .pcs_tbl = msm8996_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .clk_list = msm8996_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .regs = usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static const char * const ipq8074_pciephy_clk_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) "aux", "cfg_ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* list of resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static const char * const ipq8074_pciephy_reset_l[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) "phy", "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .type = PHY_TYPE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .serdes_tbl = ipq8074_pcie_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .tx_tbl = ipq8074_pcie_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .rx_tbl = ipq8074_pcie_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .pcs_tbl = ipq8074_pcie_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .clk_list = ipq8074_pciephy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .reset_list = ipq8074_pciephy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .vreg_list = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .num_vregs = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .regs = pciephy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .has_phy_com_ctrl = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .has_lane_rst = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .pwrdn_delay_min = 995, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .pwrdn_delay_max = 1005, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .type = PHY_TYPE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .serdes_tbl = sdm845_qmp_pcie_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .serdes_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .tx_tbl = sdm845_qmp_pcie_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .tx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .rx_tbl = sdm845_qmp_pcie_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .rx_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .pcs_tbl = sdm845_qmp_pcie_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .pcs_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .clk_list = sdm845_pciephy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .reset_list = sdm845_pciephy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .regs = sdm845_qmp_pciephy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .start_ctrl = PCS_START | SERDES_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .pwrdn_delay_min = 995, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .pwrdn_delay_max = 1005, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .type = PHY_TYPE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .serdes_tbl = sdm845_qhp_pcie_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .serdes_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .tx_tbl = sdm845_qhp_pcie_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .tx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .rx_tbl = sdm845_qhp_pcie_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .rx_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .pcs_tbl = sdm845_qhp_pcie_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .pcs_tbl_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .clk_list = sdm845_pciephy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .reset_list = sdm845_pciephy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .regs = sdm845_qhp_pciephy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .start_ctrl = PCS_START | SERDES_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .pwrdn_delay_min = 995, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .pwrdn_delay_max = 1005, /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .serdes_tbl = qmp_v3_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .tx_tbl = qmp_v3_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .rx_tbl = qmp_v3_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .pcs_tbl = qmp_v3_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .clk_list = qmp_v3_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .regs = qmp_v3_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .has_phy_dp_com_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .serdes_tbl = qmp_v3_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .tx_tbl = qmp_v3_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .rx_tbl = qmp_v3_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .pcs_tbl = qmp_v3_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .clk_list = qmp_v3_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .reset_list = sc7180_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .regs = qmp_v3_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .has_phy_dp_com_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .type = PHY_TYPE_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .serdes_tbl = qmp_v3_dp_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .tx_tbl = qmp_v3_dp_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .clk_list = qmp_v3_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .reset_list = sc7180_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .regs = qmp_v3_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .has_phy_dp_com_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .usb_cfg = &sc7180_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .dp_cfg = &sc7180_dpphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .clk_list = qmp_v3_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .regs = qmp_v3_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .type = PHY_TYPE_UFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .nlanes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .serdes_tbl = sdm845_ufsphy_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .tx_tbl = sdm845_ufsphy_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .rx_tbl = sdm845_ufsphy_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .pcs_tbl = sdm845_ufsphy_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .clk_list = sdm845_ufs_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .regs = sdm845_ufsphy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .start_ctrl = SERDES_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .no_pcs_sw_reset = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .type = PHY_TYPE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .serdes_tbl = msm8998_pcie_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .serdes_tbl_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .tx_tbl = msm8998_pcie_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .tx_tbl_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .rx_tbl = msm8998_pcie_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .rx_tbl_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .pcs_tbl = msm8998_pcie_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .pcs_tbl_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .clk_list = msm8996_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .reset_list = ipq8074_pciephy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .regs = pciephy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .serdes_tbl = msm8998_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .tx_tbl = msm8998_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .rx_tbl = msm8998_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .pcs_tbl = msm8998_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .clk_list = msm8996_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .regs = qmp_v3_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .type = PHY_TYPE_UFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .nlanes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .serdes_tbl = sm8150_ufsphy_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .tx_tbl = sm8150_ufsphy_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .rx_tbl = sm8150_ufsphy_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .pcs_tbl = sm8150_ufsphy_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .clk_list = sdm845_ufs_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .regs = sm8150_ufsphy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .start_ctrl = SERDES_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .serdes_tbl = sm8150_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .tx_tbl = sm8150_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .rx_tbl = sm8150_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .pcs_tbl = sm8150_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .clk_list = qmp_v4_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .regs = qmp_v4_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .has_phy_dp_com_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .clk_list = qmp_v4_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .regs = qmp_v4_usb3_uniphy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .serdes_tbl = sm8150_usb3_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .tx_tbl = sm8250_usb3_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .rx_tbl = sm8250_usb3_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .pcs_tbl = sm8250_usb3_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .clk_list = qmp_v4_sm8250_usbphy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .regs = qmp_v4_usb3phy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .has_phy_dp_com_ctrl = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .is_dual_lane_phy = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .type = PHY_TYPE_USB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .nlanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .clk_list = qmp_v4_phy_clk_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .reset_list = msm8996_usb3phy_reset_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .vreg_list = qmp_phy_vreg_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .regs = qmp_v4_usb3_uniphy_regs_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .start_ctrl = SERDES_START | PCS_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .pwrdn_ctrl = SW_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .has_pwrdn_delay = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static void qcom_qmp_phy_configure_lane(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) const unsigned int *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) const struct qmp_phy_init_tbl tbl[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) u8 lane_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) const struct qmp_phy_init_tbl *t = tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) for (i = 0; i < num; i++, t++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (!(t->lane_mask & lane_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (t->in_layout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) writel(t->val, base + regs[t->offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) writel(t->val, base + t->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static void qcom_qmp_phy_configure(void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) const unsigned int *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) const struct qmp_phy_init_tbl tbl[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) struct qcom_qmp *qmp = qphy->qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) void __iomem *serdes = qphy->serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) int serdes_tbl_num = cfg->serdes_tbl_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) if (cfg->type == PHY_TYPE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) switch (dp_opts->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) qcom_qmp_phy_configure(serdes, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) cfg->serdes_tbl_rbr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) cfg->serdes_tbl_rbr_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) qcom_qmp_phy_configure(serdes, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) cfg->serdes_tbl_hbr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) cfg->serdes_tbl_hbr_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) qcom_qmp_phy_configure(serdes, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) cfg->serdes_tbl_hbr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) cfg->serdes_tbl_hbr2_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) qcom_qmp_phy_configure(serdes, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) cfg->serdes_tbl_hbr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) cfg->serdes_tbl_hbr3_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) /* Other link rates aren't supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (cfg->has_phy_com_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) void __iomem *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) SERDES_START | PCS_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) mask = cfg->mask_com_pcs_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) ret = readl_poll_timeout(status, val, (val & mask), 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) PHY_INIT_COMPLETE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) dev_err(qmp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) "phy common block init timed-out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) /* Turn on BIAS current for PHY/PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) DP_PHY_PD_CTL_LANE_0_1_PWRDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) DP_PHY_PD_CTL_DP_CLAMP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) writel(QSERDES_V3_COM_BIAS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) qphy->dp_aux_cfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) PHY_AUX_REQ_ERR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) { 0x00, 0x0c, 0x14, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) { 0x00, 0x0b, 0x12, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) { 0x00, 0x0b, 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) { 0x04, 0xff, 0xff, 0xff }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) { 0x08, 0x0f, 0x16, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) { 0x11, 0x1e, 0x1f, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) { 0x19, 0x1f, 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) { 0x1f, 0xff, 0xff, 0xff }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) unsigned int v_level = 0, p_level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) u32 bias_en, drvr_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) u8 voltage_swing_cfg, pre_emphasis_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) for (i = 0; i < dp_opts->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) v_level = max(v_level, dp_opts->voltage[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) p_level = max(p_level, dp_opts->pre[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if (dp_opts->lanes == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) bias_en = 0x3e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) drvr_en = 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) bias_en = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) drvr_en = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) /* TODO: Move check to config check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) /* Enable MUX to use Cursor values from these registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) const struct phy_configure_opts_dp *dp_opts = &opts->dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) if (qphy->dp_opts.set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) qcom_qmp_phy_configure_dp_tx(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) qphy->dp_opts.set_voltages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) u32 val, phy_vco_div, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) unsigned long pixel_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) * TODO: Assume orientation is CC1 for now and two lanes, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) * use type-c connector to understand orientation and lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) * Otherwise val changes to be like below if this code understood
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) * the orientation of the type-c cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) * val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) * val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) * if (orientation == ORIENTATION_CC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) switch (dp_opts->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) phy_vco_div = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) pixel_freq = 1620000000UL / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) phy_vco_div = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) pixel_freq = 2700000000UL / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) phy_vco_div = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) pixel_freq = 5400000000UL / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) phy_vco_div = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) pixel_freq = 8100000000UL / 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) /* Other link rates aren't supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) ((status & BIT(0)) > 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) ((status & BIT(1)) > 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) udelay(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) ((status & BIT(1)) > 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) * We need to calibrate the aux setting here as many times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) * as the caller tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) qphy->dp_aux_cfg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) val = cfg1_settings[qphy->dp_aux_cfg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) struct qcom_qmp *qmp = qphy->qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) void __iomem *serdes = qphy->serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) void __iomem *pcs = qphy->pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) void __iomem *dp_com = qmp->dp_com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) mutex_lock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) if (qmp->init_count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) mutex_unlock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) /* turn on regulator supplies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) goto err_reg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) for (i = 0; i < cfg->num_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) ret = reset_control_assert(qmp->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) dev_err(qmp->dev, "%s reset assert failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) cfg->reset_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) goto err_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) for (i = cfg->num_resets - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) ret = reset_control_deassert(qmp->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) dev_err(qmp->dev, "%s reset deassert failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) qphy->cfg->reset_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) goto err_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) goto err_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) if (cfg->has_phy_dp_com_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) SW_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) /* override hardware control for reset of qmp phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) /* Default type-c orientation, i.e CC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) USB3_MODE | DP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) if (cfg->has_phy_com_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) SW_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) qphy_setbits(pcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) cfg->pwrdn_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) cfg->pwrdn_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) mutex_unlock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) err_rst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) while (++i < cfg->num_resets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) reset_control_assert(qmp->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) err_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) err_reg_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) mutex_unlock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) struct qcom_qmp *qmp = qphy->qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) void __iomem *serdes = qphy->serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) int i = cfg->num_resets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) mutex_lock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if (--qmp->init_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) mutex_unlock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) reset_control_assert(qmp->ufs_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) if (cfg->has_phy_com_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) SERDES_START | PCS_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) SW_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) reset_control_assert(qmp->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) mutex_unlock(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) static int qcom_qmp_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) struct qcom_qmp *qmp = qphy->qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) dev_vdbg(qmp->dev, "Initializing QMP phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) if (cfg->no_pcs_sw_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) * Get UFS reset, which is delayed until now to avoid a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) * circular dependency where UFS needs its PHY, but the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) * needs this UFS reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) if (!qmp->ufs_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) qmp->ufs_reset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) devm_reset_control_get_exclusive(qmp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) "ufsphy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) if (IS_ERR(qmp->ufs_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) ret = PTR_ERR(qmp->ufs_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) dev_err(qmp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) "failed to get UFS reset: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) qmp->ufs_reset = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) ret = reset_control_assert(qmp->ufs_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) ret = qcom_qmp_phy_com_init(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) if (cfg->type == PHY_TYPE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) qcom_qmp_phy_dp_aux_init(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) static int qcom_qmp_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) struct qcom_qmp *qmp = qphy->qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) void __iomem *tx = qphy->tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) void __iomem *rx = qphy->rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) void __iomem *pcs = qphy->pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) void __iomem *pcs_misc = qphy->pcs_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) void __iomem *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) unsigned int mask, val, ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) qcom_qmp_phy_serdes_init(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) if (cfg->has_lane_rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) ret = reset_control_deassert(qphy->lane_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) dev_err(qmp->dev, "lane%d reset deassert failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) qphy->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) goto err_lane_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) ret = clk_prepare_enable(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) goto err_clk_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) /* Tx, Rx, and PCS configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) qcom_qmp_phy_configure_lane(tx, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) cfg->tx_tbl, cfg->tx_tbl_num, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) /* Configuration for other LANE for USB-DP combo PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) if (cfg->is_dual_lane_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) cfg->tx_tbl, cfg->tx_tbl_num, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) /* Configure special DP tx tunings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if (cfg->type == PHY_TYPE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) qcom_qmp_phy_configure_dp_tx(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) qcom_qmp_phy_configure_lane(rx, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) cfg->rx_tbl, cfg->rx_tbl_num, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (cfg->is_dual_lane_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) cfg->rx_tbl, cfg->rx_tbl_num, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) /* Configure link rate, swing, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) if (cfg->type == PHY_TYPE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) qcom_qmp_phy_configure_dp_phy(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ret = reset_control_deassert(qmp->ufs_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) goto err_lane_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) cfg->pcs_misc_tbl_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) * Pull out PHY from POWER DOWN state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) * This is active low enable signal to power-down PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if(cfg->type == PHY_TYPE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) if (cfg->has_pwrdn_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) if (cfg->type != PHY_TYPE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) /* Pull PHY out of reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if (!cfg->no_pcs_sw_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) /* start SerDes and Phy-Coding-Sublayer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) if (cfg->type == PHY_TYPE_UFS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) mask = PCS_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) ready = PCS_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) status = pcs + cfg->regs[QPHY_PCS_STATUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) mask = PHYSTATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) ready = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) PHY_INIT_COMPLETE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) dev_err(qmp->dev, "phy initialization timed-out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) goto err_pcs_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) err_pcs_ready:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) clk_disable_unprepare(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) err_clk_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (cfg->has_lane_rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) reset_control_assert(qphy->lane_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) err_lane_rst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) static int qcom_qmp_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) clk_disable_unprepare(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) if (cfg->type == PHY_TYPE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) /* Assert DP PHY power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) /* PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) if (!cfg->no_pcs_sw_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) /* stop SerDes and Phy-Coding-Sublayer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) /* Put PHY into POWER DOWN state: active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) cfg->pwrdn_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) cfg->pwrdn_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) static int qcom_qmp_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) if (cfg->has_lane_rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) reset_control_assert(qphy->lane_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) qcom_qmp_phy_com_exit(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) static int qcom_qmp_phy_enable(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) ret = qcom_qmp_phy_init(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) ret = qcom_qmp_phy_power_on(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) qcom_qmp_phy_exit(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) static int qcom_qmp_phy_disable(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) ret = qcom_qmp_phy_power_off(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) return qcom_qmp_phy_exit(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) static int qcom_qmp_phy_set_mode(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) struct qmp_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) qphy->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) void __iomem *pcs = qphy->pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) void __iomem *pcs_misc = qphy->pcs_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) u32 intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) if (qphy->mode == PHY_MODE_USB_HOST_SS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) qphy->mode == PHY_MODE_USB_DEVICE_SS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /* Clear any pending interrupts status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) /* Writing 1 followed by 0 clears the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* Enable required PHY autonomous mode interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) /* Enable i/o clamp_n for autonomous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) if (pcs_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) void __iomem *pcs = qphy->pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) void __iomem *pcs_misc = qphy->pcs_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) /* Disable i/o clamp_n on resume for normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) if (pcs_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) /* Writing 1 followed by 0 clears the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) struct qcom_qmp *qmp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) struct qmp_phy *qphy = qmp->phys[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) /* Supported only for USB3 PHY and luckily USB3 is the first phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) if (cfg->type != PHY_TYPE_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) if (!qmp->init_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) dev_vdbg(dev, "PHY not initialized, bailing out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) qcom_qmp_phy_enable_autonomous_mode(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) clk_disable_unprepare(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) struct qcom_qmp *qmp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) struct qmp_phy *qphy = qmp->phys[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) const struct qmp_phy_cfg *cfg = qphy->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) /* Supported only for USB3 PHY and luckily USB3 is the first phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) if (cfg->type != PHY_TYPE_USB3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) if (!qmp->init_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) dev_vdbg(dev, "PHY not initialized, bailing out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) ret = clk_prepare_enable(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) qcom_qmp_phy_disable_autonomous_mode(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) struct qcom_qmp *qmp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) int num = cfg->num_vregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) if (!qmp->vregs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) qmp->vregs[i].supply = cfg->vreg_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) return devm_regulator_bulk_get(dev, num, qmp->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) struct qcom_qmp *qmp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) qmp->resets = devm_kcalloc(dev, cfg->num_resets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) sizeof(*qmp->resets), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) if (!qmp->resets)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) for (i = 0; i < cfg->num_resets; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) const char *name = cfg->reset_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) rst = devm_reset_control_get(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) dev_err(dev, "failed to get %s reset\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) qmp->resets[i] = rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) struct qcom_qmp *qmp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) int num = cfg->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) if (!qmp->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) for (i = 0; i < num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) qmp->clks[i].id = cfg->clk_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) return devm_clk_bulk_get(dev, num, qmp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) static void phy_clk_release_provider(void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) of_clk_del_provider(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) * Register a fixed rate pipe clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) * controls it. The <s>_pipe_clk coming out of the GCC is requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) * by the PHY driver for its operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) * We register the <s>_pipe_clksrc here. The gcc driver takes care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) * Below picture shows this relationship.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * | PHY block |<<---------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) * | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * | +-------+ | +-----+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) * clk | +-------+ | +-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) * +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) struct clk_fixed_rate *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) ret = of_property_read_string(np, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) init.ops = &clk_fixed_rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) /* controllers using QMP phys use 125MHz pipe clock interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) fixed->fixed_rate = 125000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) fixed->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) * Roll a devm action because the clock provider is the child node, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) * the child node is not actually a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) phy_clk_release_provider(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) * Display Port PLL driver block diagram for branch clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) * +------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) * | DP_VCO_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) * | +-------------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) * | | (DP PLL/VCO) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) * | +---------+---------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) * | v |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) * | +----------+-----------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) * | | hsclk_divsel_clk_src | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) * | +----------+-----------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) * +------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) * +---------<---------v------------>----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) * +--------v----------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) * | dp_phy_pll_link_clk | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) * | link_clk | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) * +--------+----------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) * v v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) * Input to DISPCC block |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) * for link clk, crypto clk |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) * and interface clock |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) * +--------<------------+-----------------+---<---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) * | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) * +----v---------+ +--------v-----+ +--------v------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) * | vco_divided | | vco_divided | | vco_divided |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) * | _clk_src | | _clk_src | | _clk_src |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) * | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) * |divsel_six | | divsel_two | | divsel_four |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) * +-------+------+ +-----+--------+ +--------+------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) * | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) * v---->----------v-------------<------v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) * +----------+-----------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) * | dp_phy_pll_vco_div_clk |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) * +---------+------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) * v
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) * Input to DISPCC block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) * for DP pixel clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) switch (req->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) case 1620000000UL / 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) case 2700000000UL / 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) const struct qmp_phy_dp_clks *dp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) const struct qmp_phy *qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) const struct phy_configure_opts_dp *dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) qphy = dp_clks->qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) dp_opts = &qphy->dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) switch (dp_opts->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) return 1620000000UL / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) return 2700000000UL / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) return 5400000000UL / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) return 8100000000UL / 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) switch (req->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) case 162000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) case 270000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) case 540000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) case 810000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) const struct qmp_phy_dp_clks *dp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) const struct qmp_phy *qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) const struct phy_configure_opts_dp *dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) qphy = dp_clks->qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) dp_opts = &qphy->dp_opts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) switch (dp_opts->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) return dp_opts->link_rate * 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) struct qmp_phy_dp_clks *dp_clks = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) if (idx >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) if (idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) return &dp_clks->dp_link_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) return &dp_clks->dp_pixel_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) struct qmp_phy_dp_clks *dp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) if (!dp_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) dp_clks->qphy = qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) qphy->dp_clks = dp_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) init.ops = &qcom_qmp_dp_link_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) init.name = "qmp_dp_phy_pll_link_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) dp_clks->dp_link_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) init.ops = &qcom_qmp_dp_pixel_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) init.name = "qmp_dp_phy_pll_vco_div_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) dp_clks->dp_pixel_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) * Roll a devm action because the clock provider is the child node, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) * the child node is not actually a device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) ret = devm_add_action(qmp->dev, phy_clk_release_provider, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) phy_clk_release_provider(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) static const struct phy_ops qcom_qmp_phy_gen_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) .init = qcom_qmp_phy_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) .exit = qcom_qmp_phy_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) .set_mode = qcom_qmp_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) static const struct phy_ops qcom_qmp_phy_dp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) .init = qcom_qmp_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) .configure = qcom_qmp_dp_phy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) .power_on = qcom_qmp_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) .calibrate = qcom_qmp_dp_phy_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) .power_off = qcom_qmp_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) .exit = qcom_qmp_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) .set_mode = qcom_qmp_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) .power_on = qcom_qmp_phy_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) .power_off = qcom_qmp_phy_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) .set_mode = qcom_qmp_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) void __iomem *serdes, const struct qmp_phy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) struct qcom_qmp *qmp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) struct qmp_phy *qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) const struct phy_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) char prop_name[MAX_PROP_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (!qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) qphy->cfg = cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) qphy->serdes = serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) * Get memory resources for each phy lane:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) * For single lane PHYs: pcs_misc (optional) -> 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) qphy->tx = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) if (!qphy->tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) qphy->rx = of_iomap(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) if (!qphy->rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) qphy->pcs = of_iomap(np, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) if (!qphy->pcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) * If this is a dual-lane PHY, then there should be registers for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) * second lane. Some old device trees did not specify this, so fall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) * back to old legacy behavior of assuming they can be reached at an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) * offset from the first lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) if (cfg->is_dual_lane_phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) qphy->tx2 = of_iomap(np, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) qphy->rx2 = of_iomap(np, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) if (!qphy->tx2 || !qphy->rx2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) "Underspecified device tree, falling back to legacy register regions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) /* In the old version, pcs_misc is at index 3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) qphy->pcs_misc = qphy->tx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) qphy->pcs_misc = of_iomap(np, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) qphy->pcs_misc = of_iomap(np, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) if (!qphy->pcs_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) * based phys, so they essentially have pipe clock. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) * we return error in case phy is USB3 or PIPE type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) * Otherwise, we initialize pipe clock to NULL for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) * all phys that don't need this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) if (IS_ERR(qphy->pipe_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) if (cfg->type == PHY_TYPE_PCIE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) cfg->type == PHY_TYPE_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) ret = PTR_ERR(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) "failed to get lane%d pipe_clk, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) qphy->pipe_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) /* Get lane reset, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) if (cfg->has_lane_rst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) snprintf(prop_name, sizeof(prop_name), "lane%d", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) qphy->lane_rst = of_reset_control_get(np, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) if (IS_ERR(qphy->lane_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) dev_err(dev, "failed to get lane%d reset\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) return PTR_ERR(qphy->lane_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) ops = &qcom_qmp_pcie_ufs_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) else if (cfg->type == PHY_TYPE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) ops = &qcom_qmp_phy_dp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) ops = &qcom_qmp_phy_gen_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) generic_phy = devm_phy_create(dev, np, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) ret = PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) dev_err(dev, "failed to create qphy %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) qphy->phy = generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) qphy->index = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) qphy->qmp = qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) qmp->phys[id] = qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) phy_set_drvdata(generic_phy, qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) .compatible = "qcom,ipq8074-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) .data = &ipq8074_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) .compatible = "qcom,msm8996-qmp-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) .data = &msm8996_pciephy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) .compatible = "qcom,msm8996-qmp-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) .data = &msm8996_ufs_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) .compatible = "qcom,msm8996-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) .data = &msm8996_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) .compatible = "qcom,msm8998-qmp-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) .data = &msm8998_pciephy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) .compatible = "qcom,msm8998-qmp-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) .data = &sdm845_ufsphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) .compatible = "qcom,ipq8074-qmp-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) .data = &ipq8074_pciephy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) .compatible = "qcom,sc7180-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) .data = &sc7180_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) /* It's a combo phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) .compatible = "qcom,sdm845-qhp-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) .data = &sdm845_qhp_pciephy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) .compatible = "qcom,sdm845-qmp-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) .data = &sdm845_qmp_pciephy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) .compatible = "qcom,sdm845-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) .data = &qmp_v3_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) .data = &qmp_v3_usb3_uniphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) .compatible = "qcom,sdm845-qmp-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) .data = &sdm845_ufsphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) .compatible = "qcom,msm8998-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) .data = &msm8998_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) .compatible = "qcom,sm8150-qmp-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) .data = &sm8150_ufsphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) .compatible = "qcom,sm8250-qmp-ufs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) .data = &sm8150_ufsphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) .compatible = "qcom,sm8150-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) .data = &sm8150_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) .data = &sm8150_usb3_uniphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) .compatible = "qcom,sm8250-qmp-usb3-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) .data = &sm8250_usb3phy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) .data = &sm8250_usb3_uniphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) .data = &sc7180_usb3dpphy_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) qcom_qmp_phy_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) static int qcom_qmp_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) struct qcom_qmp *qmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) void __iomem *serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) void __iomem *usb_serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) void __iomem *dp_serdes = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) const struct qmp_phy_combo_cfg *combo_cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) const struct qmp_phy_cfg *cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) const struct qmp_phy_cfg *usb_cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) const struct qmp_phy_cfg *dp_cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) int num, id, expected_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) if (!qmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) qmp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) dev_set_drvdata(dev, qmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) /* Get the specific init parameters of QMP phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) cfg = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) combo_cfg = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) if (!combo_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) usb_cfg = combo_cfg->usb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) cfg = usb_cfg; /* Setup clks and regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) /* per PHY serdes; usually located at base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) if (IS_ERR(serdes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) return PTR_ERR(serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) /* per PHY dp_com; if PHY has dp_com control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) if (IS_ERR(qmp->dp_com))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) return PTR_ERR(qmp->dp_com);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) if (combo_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) /* Only two serdes for combo PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) dp_serdes = devm_platform_ioremap_resource(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) if (IS_ERR(dp_serdes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) return PTR_ERR(dp_serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) dp_cfg = combo_cfg->dp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) expected_phys = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) expected_phys = cfg->nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) mutex_init(&qmp->phy_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) ret = qcom_qmp_phy_clk_init(dev, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) ret = qcom_qmp_phy_reset_init(dev, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) ret = qcom_qmp_phy_vreg_init(dev, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) dev_err(dev, "failed to get regulator supplies: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) num = of_get_available_child_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) /* do we have a rogue child node ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) if (num > expected_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) if (!qmp->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) * Prevent runtime pm from being ON by default. Users can enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) * it using power/control in sysfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) pm_runtime_forbid(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) for_each_available_child_of_node(dev->of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) if (of_node_name_eq(child, "dp-phy")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) cfg = dp_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) serdes = dp_serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) } else if (of_node_name_eq(child, "usb3-phy")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) cfg = usb_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) serdes = usb_serdes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) /* Create per-lane phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) dev_err(dev, "failed to create lane%d phy, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) goto err_node_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) * Register the pipe clock provided by phy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) * See function description to see details of this pipe clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) ret = phy_pipe_clk_register(qmp, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) dev_err(qmp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) "failed to register pipe clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) goto err_node_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) } else if (cfg->type == PHY_TYPE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) dev_err(qmp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) "failed to register DP clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) goto err_node_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) if (!IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) dev_info(dev, "Registered Qcom-QMP phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) err_node_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) static struct platform_driver qcom_qmp_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) .probe = qcom_qmp_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) .name = "qcom-qmp-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) .pm = &qcom_qmp_phy_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) .of_match_table = qcom_qmp_phy_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) module_platform_driver(qcom_qmp_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags