^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCIE20_PARF_PHY_STTS 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCIE2_PHY_RESET_CTRL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCIE20_PARF_PHY_REFCLK_CTRL2 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIE20_PARF_PHY_REFCLK_CTRL3 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIE20_PARF_PCS_SWING_CTRL1 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCIE20_PARF_PCS_SWING_CTRL2 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCIE20_PARF_PCS_DEEMPH1 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIE20_PARF_PCS_DEEMPH2 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIE20_PARF_PCS_DEEMPH3 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCIE20_PARF_CONFIGBITS 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCIE20_PARF_PHY_CTRL3 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIE20_PARF_PCS_CTRL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TX_AMP_VAL 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_RX0_EQ_GEN1_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_RX0_EQ_GEN2_VAL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TX_DEEMPH_GEN1_VAL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TX_DEEMPH_GEN2_3_5DB_VAL 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TX_DEEMPH_GEN2_6DB_VAL 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_TX0_TERM_OFFST_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct qcom_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct regulator_bulk_data vregs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct reset_control *phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct reset_control *pipe_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *pipe_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int qcom_pcie2_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct qcom_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = reset_control_deassert(qphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(qphy->dev, "cannot deassert pipe reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reset_control_assert(qphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int qcom_pcie2_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct qcom_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Program REF_CLK source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Don't use PAD for refclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Program SSP ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) val |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Assert Phy SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Program Tx Amplitude */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val &= ~0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val |= TX_AMP_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val &= ~0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val |= TX_AMP_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Program De-Emphasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val &= ~0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val |= TX_DEEMPH_GEN2_6DB_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val |= TX_DEEMPH_GEN2_3_5DB_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val &= ~0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val |= TX_DEEMPH_GEN1_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Program Rx_Eq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val &= ~0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= PHY_RX0_EQ_GEN2_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Program Tx0_term_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) val &= ~0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) val |= PHY_TX0_TERM_OFFST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* disable Tx2Rx Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) val &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* De-assert Phy SW Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = reset_control_deassert(qphy->pipe_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(qphy->dev, "cannot deassert pipe reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) clk_set_rate(qphy->pipe_clk, 250000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = clk_prepare_enable(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(qphy->dev, "failed to enable pipe clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) !(val & BIT(0)), 1000, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(qphy->dev, "phy initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int qcom_pcie2_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct qcom_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk_disable_unprepare(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reset_control_assert(qphy->pipe_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int qcom_pcie2_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct qcom_phy *qphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reset_control_assert(qphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct phy_ops qcom_pcie2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .init = qcom_pcie2_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .power_on = qcom_pcie2_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .power_off = qcom_pcie2_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .exit = qcom_pcie2_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Register a fixed rate pipe clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * controls it. The <s>_pipe_clk coming out of the GCC is requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * by the PHY driver for its operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * We register the <s>_pipe_clksrc here. The gcc driver takes care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Below picture shows this relationship.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * | PHY block |<<---------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * | +-------+ | +-----+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * clk | +-------+ | +-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * +---------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct device_node *np = qphy->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct clk_fixed_rate *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = of_property_read_string(np, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(qphy->dev, "%s: No clock-output-names\n", np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) init.ops = &clk_fixed_rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* controllers using QMP phys use 250MHz pipe clock interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) fixed->fixed_rate = 250000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) fixed->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return devm_clk_hw_register(qphy->dev, &fixed->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int qcom_pcie2_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct qcom_phy *qphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!qphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) qphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) qphy->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (IS_ERR(qphy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return PTR_ERR(qphy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = phy_pipe_clksrc_register(qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(dev, "failed to register pipe_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) qphy->vregs[0].supply = "vdda-vp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) qphy->vregs[1].supply = "vdda-vph";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) qphy->pipe_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (IS_ERR(qphy->pipe_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(dev, "failed to acquire pipe clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return PTR_ERR(qphy->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (IS_ERR(qphy->phy_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_err(dev, "failed to acquire phy reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return PTR_ERR(qphy->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (IS_ERR(qphy->pipe_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(dev, "failed to acquire pipe reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return PTR_ERR(qphy->pipe_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) phy = devm_phy_create(dev, dev->of_node, &qcom_pcie2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(dev, "failed to create phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) phy_set_drvdata(phy, qphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(dev, "failed to register phy provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct of_device_id qcom_pcie2_phy_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { .compatible = "qcom,pcie2-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_DEVICE_TABLE(of, qcom_pcie2_phy_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct platform_driver qcom_pcie2_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .probe = qcom_pcie2_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = "phy-qcom-pcie2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .of_match_table = qcom_pcie2_phy_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) module_platform_driver(qcom_pcie2_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DESCRIPTION("Qualcomm PCIe PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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