^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* USB QSCRATCH Hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define QSCRATCH_GENERAL_CFG (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HSUSB_PHY_CTRL_REG (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* PHY_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HSUSB_CTRL_DMSEHV_CLAMP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HSUSB_CTRL_USB2_SUSPEND BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HSUSB_CTRL_UTMI_CLK_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HSUSB_CTRL_USE_CLKCORE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HSUSB_CTRL_DPSEHV_CLAMP BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HSUSB_CTRL_COMMONONN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HSUSB_CTRL_ID_HV_CLAMP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HSUSB_CTRL_CLAMP_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HSUSB_CTRL_RETENABLEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HSUSB_CTRL_POR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* QSCRATCH_GENERAL_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HSUSB_GCFG_XHCI_REV BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* USB QSCRATCH Hardware registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SSUSB_PHY_CTRL_REG (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SSUSB_PHY_PARAM_CTRL_1 (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SSUSB_PHY_PARAM_CTRL_2 (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CR_PROTOCOL_DATA_IN_REG (0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CR_PROTOCOL_DATA_OUT_REG (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CR_PROTOCOL_CAP_ADDR_REG (0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CR_PROTOCOL_CAP_DATA_REG (0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CR_PROTOCOL_READ_REG (0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CR_PROTOCOL_WRITE_REG (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* PHY_CTRL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SSUSB_CTRL_REF_USE_PAD BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SSUSB_CTRL_TEST_POWERDOWN BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SSUSB_CTRL_SS_PHY_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SSUSB_CTRL_SS_PHY_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* SSPHY control registers - Does this need 0x30? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * (lane))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* SSPHY SoC version specific values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SSPHY_RX_EQ_VALUE 4 /* Override value for rx_eq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Override value for transmit preemphasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SSPHY_TX_DEEMPH_3_5DB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Override value for mpll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SSPHY_MPLL_VALUE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* QSCRATCH PHY_PARAM_CTRL1 fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK GENMASK(26, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK GENMASK(19, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK GENMASK(13, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_PARAM_CTRL1_LOS_BIAS_MASK GENMASK(7, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_PARAM_CTRL1_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PHY_PARAM_CTRL1_LOS_BIAS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_PARAM_CTRL1_TX_FULL_SWING(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (((x) << 8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_PARAM_CTRL1_LOS_BIAS(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (((x) << 3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* RX OVRD IN HI bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RX_OVRD_IN_HI_RX_RX_RESET BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RX_OVRD_IN_HI_RX_EQ_MASK GENMASK(10, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RX_OVRD_IN_HI_RX_EQ(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RX_OVRD_IN_HI_RX_EQ_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK GENMASK(4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RX_OVRD_IN_HI_RX_RATE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* TX OVRD DRV LO register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TX_OVRD_DRV_LO_AMPLITUDE_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TX_OVRD_DRV_LO_PREEMPH_MASK GENMASK(13, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TX_OVRD_DRV_LO_PREEMPH(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TX_OVRD_DRV_LO_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* MPLL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SSPHY_MPLL_MASK GENMASK(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SSPHY_MPLL(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* SS CAP register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SS_CR_CAP_ADDR_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SS_CR_CAP_DATA_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SS_CR_READ_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SS_CR_WRITE_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct usb_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk *xo_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 rx_eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 tx_deamp_3_5db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 mpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct phy_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct phy_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Write register and read back masked value to confirm it is written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @base - QCOM DWC3 PHY base virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @offset - register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @mask - register bitmask specifying what should be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @val - value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 write_val, tmp = readl(phy_dwc3->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tmp &= ~mask; /* retain other bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) write_val = tmp | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(write_val, phy_dwc3->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Read back to see if val was written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tmp = readl(phy_dwc3->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp &= mask; /* clear other bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (tmp != val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int wait_for_latch(void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 retry = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!readl(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (--retry == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Write SSPHY register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @base - QCOM DWC3 PHY base virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @addr - SSPHY address to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @val - value to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(SS_CR_CAP_ADDR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto err_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writel(SS_CR_CAP_DATA_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto err_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Read SSPHY register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @base - QCOM DWC3 PHY base virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @addr - SSPHY address to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 addr, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(SS_CR_CAP_ADDR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto err_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Due to hardware bug, first read of SSPHY register might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * incorrect. Hence as workaround, SW should perform SSPHY register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * read twice, but use only second read and ignore first read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto err_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* throwaway read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) goto err_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err_wait:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = clk_prepare_enable(phy_dwc3->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = clk_prepare_enable(phy_dwc3->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) clk_disable_unprepare(phy_dwc3->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * enable clamping, and disable RETENTION (power-on default is ENABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) HSUSB_CTRL_RETENABLEN | HSUSB_CTRL_COMMONONN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* use core clock if external reference is not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!phy_dwc3->xo_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val |= HSUSB_CTRL_USE_CLKCORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) usleep_range(2000, 2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Disable (bypass) VBUS and ID filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) clk_disable_unprepare(phy_dwc3->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk_disable_unprepare(phy_dwc3->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = clk_prepare_enable(phy_dwc3->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = clk_prepare_enable(phy_dwc3->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk_disable_unprepare(phy_dwc3->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* reset phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(data | SSUSB_CTRL_SS_PHY_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) phy_dwc3->base + SSUSB_PHY_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) usleep_range(2000, 2200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* clear REF_PAD if we don't have XO clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!phy_dwc3->xo_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) data &= ~SSUSB_CTRL_REF_USE_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) data |= SSUSB_CTRL_REF_USE_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* wait for ref clk to become stable, this can take up to 30ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * in HS mode instead of SS mode. Workaround it by asserting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) data |= (1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) data &= ~0xff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) data |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Fix RX Equalization setting as follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = usb_ss_write_phycreg(phy_dwc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Set EQ and TX launch amplitudes as follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * LANE0.TX_OVRD_DRV_LO.EN set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = usb_ss_read_phycreg(phy_dwc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) data |= 0x6E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) data |= TX_OVRD_DRV_LO_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = usb_ss_write_phycreg(phy_dwc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) goto err_phy_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) data &= ~SSPHY_MPLL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) data |= SSPHY_MPLL(phy_dwc3->mpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) usb_ss_write_phycreg(phy_dwc3, 0x30, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * TX_FULL_SWING [26:20] amplitude to 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * TX_DEEMPH_6DB [19:14] to 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * TX_DEEMPH_3_5DB [13:8] set based on SoC version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * LOS_BIAS [7:3] to 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) data &= ~PHY_PARAM_CTRL1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PHY_PARAM_CTRL1_LOS_BIAS(0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PHY_PARAM_CTRL1_MASK, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err_phy_trans:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Sequence to put SSPHY in low power state:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * 1. Clear REF_PHY_EN in PHY_CTRL_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * 2. Clear REF_USE_PAD in PHY_CTRL_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) SSUSB_CTRL_SS_PHY_EN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SSUSB_CTRL_REF_USE_PAD, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SSUSB_CTRL_TEST_POWERDOWN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clk_disable_unprepare(phy_dwc3->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) clk_disable_unprepare(phy_dwc3->xo_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .init = qcom_ipq806x_usb_hs_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .exit = qcom_ipq806x_usb_hs_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .clk_rate = 60000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .init = qcom_ipq806x_usb_ss_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .exit = qcom_ipq806x_usb_ss_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .clk_rate = 125000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { .compatible = "qcom,ipq806x-usb-phy-hs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .data = &qcom_ipq806x_usb_hs_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .compatible = "qcom,ipq806x-usb-phy-ss",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .data = &qcom_ipq806x_usb_ss_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct usb_phy *phy_dwc3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const struct phy_drvdata *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!phy_dwc3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) phy_dwc3->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!phy_dwc3->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(phy_dwc3->dev, "failed to map reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (IS_ERR(phy_dwc3->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return PTR_ERR(phy_dwc3->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (IS_ERR(phy_dwc3->xo_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) phy_dwc3->xo_clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Parse device node to probe HSIO settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &phy_dwc3->rx_eq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) &phy_dwc3->tx_deamp_3_5db))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) phy_dwc3->mpll = SSPHY_MPLL_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (IS_ERR(generic_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) phy_set_drvdata(generic_phy, phy_dwc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) platform_set_drvdata(pdev, phy_dwc3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static struct platform_driver qcom_ipq806x_usb_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .probe = qcom_ipq806x_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .name = "qcom-ipq806x-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .of_match_table = qcom_ipq806x_usb_phy_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) module_platform_driver(qcom_ipq806x_usb_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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