^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct qcom_ipq806x_sata_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk *cfg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SATA_PHY_P0_PARAM0 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(x) __set(x, 17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2(x) __set(x, 11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1(x) __set(x, 5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SATA_PHY_P0_PARAM1 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SATA_PHY_P0_PARAM1_RESERVED_BITS31_21(x) __set(x, 31, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(x) __set(x, 20, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(x) __set(x, 13, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(x) __set(x, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SATA_PHY_P0_PARAM2 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SATA_PHY_P0_PARAM2_RX_EQ(x) __set(x, 20, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SATA_PHY_P0_PARAM3 0x20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SATA_PHY_SSC_EN 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SATA_PHY_P0_PARAM4 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SATA_PHY_REF_SSP_EN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SATA_PHY_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int qcom_ipq806x_sata_phy_init(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Setting SSC_EN to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg = reg | SATA_PHY_SSC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ~(SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg |= SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3(0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ~(SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg |= SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3(0x55) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2(0x55) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1(0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ~SATA_PHY_P0_PARAM2_RX_EQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg |= SATA_PHY_P0_PARAM2_RX_EQ(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Setting PHY_RESET to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg = reg | SATA_PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Setting REF_SSP_EN to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = reg | SATA_PHY_REF_SSP_EN | SATA_PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* make sure all changes complete before we let the PHY out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* sleep for max. 50us more to combine processor wakeups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) usleep_range(20, 20 + 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Clearing PHY_RESET to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = reg & ~SATA_PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int qcom_ipq806x_sata_phy_exit(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct qcom_ipq806x_sata_phy *phy = phy_get_drvdata(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Setting PHY_RESET to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg = reg | SATA_PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct phy_ops qcom_ipq806x_sata_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .init = qcom_ipq806x_sata_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .exit = qcom_ipq806x_sata_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int qcom_ipq806x_sata_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct qcom_ipq806x_sata_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) phy->mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (IS_ERR(phy->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return PTR_ERR(phy->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) generic_phy = devm_phy_create(dev, NULL, &qcom_ipq806x_sata_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(dev, "%s: failed to create phy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) phy_set_drvdata(generic_phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) platform_set_drvdata(pdev, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) phy->cfg_clk = devm_clk_get(dev, "cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (IS_ERR(phy->cfg_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(dev, "Failed to get sata cfg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return PTR_ERR(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = clk_prepare_enable(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_disable_unprepare(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(dev, "%s: failed to register phy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int qcom_ipq806x_sata_phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct qcom_ipq806x_sata_phy *phy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clk_disable_unprepare(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct of_device_id qcom_ipq806x_sata_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .compatible = "qcom,ipq806x-sata-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DEVICE_TABLE(of, qcom_ipq806x_sata_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct platform_driver qcom_ipq806x_sata_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .probe = qcom_ipq806x_sata_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .remove = qcom_ipq806x_sata_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "qcom-ipq806x-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .of_match_table = qcom_ipq806x_sata_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) module_platform_driver(qcom_ipq806x_sata_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_DESCRIPTION("QCOM IPQ806x SATA PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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