^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNIPHY_PLL_REFCLK_CFG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNIPHY_PLL_PWRGEN_CFG 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UNIPHY_PLL_GLB_CFG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UNIPHY_PLL_SDM_CFG0 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UNIPHY_PLL_SDM_CFG1 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UNIPHY_PLL_SDM_CFG2 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UNIPHY_PLL_SDM_CFG3 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UNIPHY_PLL_SDM_CFG4 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UNIPHY_PLL_SSC_CFG0 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UNIPHY_PLL_SSC_CFG1 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UNIPHY_PLL_SSC_CFG2 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UNIPHY_PLL_SSC_CFG3 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNIPHY_PLL_LKDET_CFG0 0x05C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UNIPHY_PLL_LKDET_CFG1 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UNIPHY_PLL_LKDET_CFG2 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UNIPHY_PLL_CAL_CFG0 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNIPHY_PLL_CAL_CFG8 0x08C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UNIPHY_PLL_CAL_CFG9 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UNIPHY_PLL_CAL_CFG10 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UNIPHY_PLL_CAL_CFG11 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UNIPHY_PLL_STATUS 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SATA_PHY_SER_CTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SATA_PHY_TX_DRIV_CTRL0 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SATA_PHY_TX_DRIV_CTRL1 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SATA_PHY_TX_IMCAL0 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SATA_PHY_TX_IMCAL2 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SATA_PHY_RX_IMCAL0 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SATA_PHY_EQUAL 0x13C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SATA_PHY_OOB_TERM 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SATA_PHY_CDR_CTRL0 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SATA_PHY_CDR_CTRL1 0x14C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SATA_PHY_CDR_CTRL2 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SATA_PHY_CDR_CTRL3 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SATA_PHY_PI_CTRL0 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SATA_PHY_POW_DWN_CTRL0 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SATA_PHY_POW_DWN_CTRL1 0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SATA_PHY_TX_DATA_CTRL 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SATA_PHY_ALIGNP 0x1A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SATA_PHY_TX_IMCAL_STAT 0x1E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SATA_PHY_RX_IMCAL_STAT 0x1E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UNIPHY_PLL_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SATA_PHY_TX_CAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SATA_PHY_RX_CAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* default timeout set to 1 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TIMEOUT_MS 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DELAY_INTERVAL_US 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct qcom_apq8064_sata_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *cfg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Helper function to do poll and timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int poll_timeout(void __iomem *addr, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return readl_relaxed_poll_timeout(addr, val, (val & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DELAY_INTERVAL_US, TIMEOUT_MS * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int qcom_apq8064_sata_phy_init(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *base = phy->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* SATA phy initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Make sure the power down happens before power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) usleep_range(10, 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Write UNIPHYPLL registers to configure PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel_relaxed(0xF3, base + UNIPHY_PLL_CAL_CFG8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel_relaxed(0x01, base + UNIPHY_PLL_CAL_CFG9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(0xED, base + UNIPHY_PLL_CAL_CFG10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel_relaxed(0x02, base + UNIPHY_PLL_CAL_CFG11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel_relaxed(0x36, base + UNIPHY_PLL_SDM_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel_relaxed(0x0D, base + UNIPHY_PLL_SDM_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel_relaxed(0xA3, base + UNIPHY_PLL_SDM_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel_relaxed(0xF0, base + UNIPHY_PLL_SDM_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel_relaxed(0x00, base + UNIPHY_PLL_SDM_CFG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel_relaxed(0x19, base + UNIPHY_PLL_SSC_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel_relaxed(0xE1, base + UNIPHY_PLL_SSC_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel_relaxed(0x00, base + UNIPHY_PLL_SSC_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel_relaxed(0x11, base + UNIPHY_PLL_SSC_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel_relaxed(0x04, base + UNIPHY_PLL_LKDET_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel_relaxed(0xFF, base + UNIPHY_PLL_LKDET_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel_relaxed(0x02, base + UNIPHY_PLL_GLB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* make sure global config LDO power down happens before power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(0x03, base + UNIPHY_PLL_GLB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(0x05, base + UNIPHY_PLL_LKDET_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* PLL Lock wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = poll_timeout(base + UNIPHY_PLL_STATUS, UNIPHY_PLL_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(phy->dev, "poll timeout UNIPHY_PLL_STATUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* TX Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = poll_timeout(base + SATA_PHY_TX_IMCAL_STAT, SATA_PHY_TX_CAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(phy->dev, "poll timeout SATA_PHY_TX_IMCAL_STAT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* RX Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = poll_timeout(base + SATA_PHY_RX_IMCAL_STAT, SATA_PHY_RX_CAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(phy->dev, "poll timeout SATA_PHY_RX_IMCAL_STAT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* SATA phy calibrated succesfully, power up to functional mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel_relaxed(0x00, base + SATA_PHY_POW_DWN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writel_relaxed(0x59, base + SATA_PHY_CDR_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) writel_relaxed(0x04, base + SATA_PHY_CDR_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel_relaxed(0x00, base + SATA_PHY_PI_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel_relaxed(0x00, base + SATA_PHY_CDR_CTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel_relaxed(0x11, base + SATA_PHY_TX_DATA_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel_relaxed(0x43, base + SATA_PHY_ALIGNP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writel_relaxed(0x04, base + SATA_PHY_OOB_TERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel_relaxed(0x01, base + SATA_PHY_EQUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel_relaxed(0x09, base + SATA_PHY_TX_DRIV_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int qcom_apq8064_sata_phy_exit(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct qcom_apq8064_sata_phy *phy = phy_get_drvdata(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *base = phy->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Power down PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel_relaxed(0xF8, base + SATA_PHY_POW_DWN_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel_relaxed(0xFE, base + SATA_PHY_POW_DWN_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Power down PLL block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel_relaxed(0x00, base + UNIPHY_PLL_GLB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct phy_ops qcom_apq8064_sata_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .init = qcom_apq8064_sata_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .exit = qcom_apq8064_sata_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct qcom_apq8064_sata_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) phy->mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (IS_ERR(phy->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return PTR_ERR(phy->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) generic_phy = devm_phy_create(dev, NULL, &qcom_apq8064_sata_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_err(dev, "%s: failed to create phy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) phy_set_drvdata(generic_phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) platform_set_drvdata(pdev, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) phy->cfg_clk = devm_clk_get(dev, "cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (IS_ERR(phy->cfg_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(dev, "Failed to get sata cfg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return PTR_ERR(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = clk_prepare_enable(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clk_disable_unprepare(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_err(dev, "%s: failed to register phy\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int qcom_apq8064_sata_phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct qcom_apq8064_sata_phy *phy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_disable_unprepare(phy->cfg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct of_device_id qcom_apq8064_sata_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .compatible = "qcom,apq8064-sata-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MODULE_DEVICE_TABLE(of, qcom_apq8064_sata_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct platform_driver qcom_apq8064_sata_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .probe = qcom_apq8064_sata_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .remove = qcom_apq8064_sata_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "qcom-apq8064-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .of_match_table = qcom_apq8064_sata_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) module_platform_driver(qcom_apq8064_sata_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_DESCRIPTION("QCOM apq8064 SATA PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags