^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AppliedMicro X-Gene Multi-purpose PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Loc Ho <lho@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Tuan Phan <tphan@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Suman Tripathi <stripathi@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The first PLL clock macro is used for internal reference clock. The second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * PLL clock macro is used to generate the clock for the PHY. This driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * operate according to the mode of operation. The first PLL CMU is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * required if internal clock is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Logical Layer Out Of HW module units:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | Internal | |------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | Ref PLL CMU |----| | ------------- ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * | | | | ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * External Clock ------| | -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * |------|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The Ref PLL CMU CSR (Configuration System Registers) is accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * indirectly from the SDS offset at 0x2000. It is only required for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * internal reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * it is located outside the PHY IP. This is the case for the PHY located
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Currently, this driver only supports Gen3 SATA mode with external clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Max 2 lanes per a PHY unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX_LANE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Register offset inside the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SERDES_PLL_INDIRECT_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SERDES_INDIRECT_OFFSET 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SERDES_LANE_STRIDE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Some default Serdes parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DEFAULT_SATA_TXEYEDIRECTION { 0x0, 0x0, 0x0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DEFAULT_SATA_TXEYETUNING { 0xa, 0xa, 0xa }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DEFAULT_SATA_SPD_SEL { 0x1, 0x3, 0x7 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DEFAULT_SATA_TXAMP { 0x8, 0x8, 0x8 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DEFAULT_SATA_TXCN1 { 0x2, 0x2, 0x2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEFAULT_SATA_TXCN2 { 0x0, 0x0, 0x0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DEFAULT_SATA_TXCP1 { 0xa, 0xa, 0xa }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SATA_SPD_SEL_GEN3 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SATA_SPD_SEL_GEN2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SATA_SPD_SEL_GEN1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SSC_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SSC_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FBDIV_VAL_50M 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REFDIV_VAL_50M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FBDIV_VAL_100M 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REFDIV_VAL_100M 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SATA Clock/Reset CSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SATACLKENREG 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SATA0_CORE_CLKEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SATA1_CORE_CLKEN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SATASRESETREG 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SATA_MEM_RESET_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SATA_SDS_RESET_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SATA_CSR_RESET_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SATA_CORE_RESET_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SATA_PMCLK_RESET_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SATA_PCLK_RESET_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* SDS CSR used for PHY Indirect access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SATA_ENET_SDS_PCS_CTL0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SATA_ENET_SDS_CTL0 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SATA_ENET_SDS_CTL1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SATA_ENET_SDS_RST_CTL 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SATA_ENET_SDS_IND_CMD_REG 0x0000003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CFG_IND_WR_CMD_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CFG_IND_RD_CMD_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CFG_IND_CMD_DONE_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CFG_IND_ADDR_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SATA_ENET_SDS_IND_RDATA_REG 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SATA_ENET_SDS_IND_WDATA_REG 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SATA_ENET_CLK_MACRO_REG 0x0000004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define I_RESET_B_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define I_PLL_FBDIV_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I_CUSTOMEROV_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CMU_REG0 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CMU_REG0_PLL_REF_SEL_MASK 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CMU_REG0_PDOWN_MASK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMU_REG1 0x00002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMU_REG1_PLL_CP_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CMU_REG1_REFCLK_CMOS_SEL_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMU_REG2 0x00004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMU_REG2_PLL_REFDIV_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMU_REG2_PLL_LFRES_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMU_REG2_PLL_FBDIV_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMU_REG3 0x00006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CMU_REG3_VCOVARSEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMU_REG4 0x00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CMU_REG5 0x0000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CMU_REG5_PLL_LFCAP_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CMU_REG5_PLL_RESETB_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CMU_REG6 0x0000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CMU_REG7 0x0000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMU_REG8 0x00010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CMU_REG9 0x00012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CMU_REG9_WORD_LEN_8BIT 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CMU_REG9_WORD_LEN_10BIT 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CMU_REG9_WORD_LEN_16BIT 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CMU_REG9_WORD_LEN_20BIT 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CMU_REG9_WORD_LEN_32BIT 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CMU_REG9_WORD_LEN_40BIT 0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CMU_REG9_WORD_LEN_64BIT 0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CMU_REG9_WORD_LEN_66BIT 0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CMU_REG10 0x00014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CMU_REG10_VREG_REFSEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CMU_REG11 0x00016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CMU_REG12 0x00018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CMU_REG12_STATE_DELAY9_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMU_REG13 0x0001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CMU_REG14 0x0001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CMU_REG15 0x0001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CMU_REG16 0x00020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CMU_REG16_PVT_DN_MAN_ENA_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CMU_REG16_PVT_UP_MAN_ENA_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CMU_REG17 0x00022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CMU_REG17_RESERVED_7_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CMU_REG17_PVT_TERM_MAN_ENA_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CMU_REG18 0x00024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CMU_REG19 0x00026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CMU_REG20 0x00028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CMU_REG21 0x0002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CMU_REG22 0x0002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CMU_REG23 0x0002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CMU_REG24 0x00030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CMU_REG25 0x00032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CMU_REG26 0x00034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CMU_REG27 0x00036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CMU_REG28 0x00038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CMU_REG29 0x0003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CMU_REG30 0x0003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CMU_REG30_LOCK_COUNT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CMU_REG30_PCIE_MODE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CMU_REG31 0x0003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CMU_REG32 0x00040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CMU_REG32_FORCE_VCOCAL_START_MASK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CMU_REG32_IREF_ADJ_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CMU_REG33 0x00042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CMU_REG34 0x00044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CMU_REG35 0x00046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CMU_REG36 0x00048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CMU_REG37 0x0004a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CMU_REG38 0x0004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CMU_REG39 0x0004e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* PHY lane CSR accessing from SDS indirectly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define RXTX_REG0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define RXTX_REG1 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define RXTX_REG1_RXACVCM_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RXTX_REG1_CTLE_EQ_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define RXTX_REG1_RXVREG1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define RXTX_REG2 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define RXTX_REG2_VTT_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define RXTX_REG2_VTT_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define RXTX_REG4 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define RXTX_REG5 0x00a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define RXTX_REG5_TX_CN1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define RXTX_REG5_TX_CP1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define RXTX_REG5_TX_CN2_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define RXTX_REG6 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RXTX_REG6_TX_IDLE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RXTX_REG7 0x00e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RXTX_REG7_RESETB_RXD_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RXTX_REG7_RESETB_RXA_MASK 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RXTX_REG8 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define RXTX_REG8_SD_VREF_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define RXTX_REG8_SD_DISABLE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define RXTX_REG7 0x00e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define RXTX_REG7_RESETB_RXD_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define RXTX_REG7_RESETB_RXA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define RXTX_REG11 0x016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define RXTX_REG12 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define RXTX_REG12_RX_DET_TERM_ENABLE_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define RXTX_REG13 0x01a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define RXTX_REG14 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define RXTX_REG26 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define RXTX_REG26_BLWC_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define RXTX_REG21 0x02a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define RXTX_REG22 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define RXTX_REG23 0x02e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define RXTX_REG24 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define RXTX_REG27 0x036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define RXTX_REG28 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define RXTX_REG31 0x03e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define RXTX_REG38 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define RXTX_REG39 0x04e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define RXTX_REG40 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define RXTX_REG41 0x052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define RXTX_REG42 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define RXTX_REG43 0x056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define RXTX_REG44 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define RXTX_REG45 0x05a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define RXTX_REG46 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define RXTX_REG47 0x05e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define RXTX_REG48 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define RXTX_REG49 0x062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define RXTX_REG50 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define RXTX_REG51 0x066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define RXTX_REG52 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define RXTX_REG53 0x06a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define RXTX_REG54 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define RXTX_REG55 0x06e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define RXTX_REG61 0x07a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define RXTX_REG62 0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define RXTX_REG81 0x0a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define RXTX_REG89_MU_TH7_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define RXTX_REG89_MU_TH8_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define RXTX_REG89_MU_TH9_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define RXTX_REG96 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define RXTX_REG96_MU_FREQ1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define RXTX_REG96_MU_FREQ2_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define RXTX_REG96_MU_FREQ3_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define RXTX_REG99 0x0c6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define RXTX_REG99_MU_PHASE1_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define RXTX_REG99_MU_PHASE2_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define RXTX_REG99_MU_PHASE3_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define RXTX_REG102 0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define RXTX_REG114 0x0e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define RXTX_REG121 0x0f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define RXTX_REG125 0x0fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define RXTX_REG125_PQ_REG_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define RXTX_REG125_SIGN_PQ_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define RXTX_REG127 0x0fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define RXTX_REG127_FORCE_SUM_CAL_START_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define RXTX_REG127_FORCE_LAT_CAL_START_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define RXTX_REG128 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define RXTX_REG129 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define RXTX_REG130 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define RXTX_REG145 0x122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RXTX_REG145_RXES_ENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define RXTX_REG147 0x126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define RXTX_REG148 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Clock macro type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) enum cmu_type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) REF_CMU = 0, /* Clock macro is the internal reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PHY_CMU = 1, /* Clock macro is the PLL for the Serdes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) enum mux_type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MUX_SELECT_ATA = 0, /* Switch the MUX to ATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MUX_SELECT_SGMMII = 0, /* Switch the MUX to SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) enum clk_type_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) CLK_EXT_DIFF = 0, /* External differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) CLK_INT_DIFF = 1, /* Internal differential */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) CLK_INT_SING = 2, /* Internal single ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enum xgene_phy_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODE_SATA = 0, /* List them for simple reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODE_SGMII = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODE_PCIE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODE_USB = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MODE_XFI = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MODE_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct xgene_sata_override_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 speed[MAX_LANE]; /* Index for override parameter per lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 txspeed[3]; /* Tx speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 txboostgain[MAX_LANE*3]; /* Tx freq boost and gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 txeyetuning[MAX_LANE*3]; /* Tx eye tuning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 txeyedirection[MAX_LANE*3]; /* Tx eye tuning direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 txamplitude[MAX_LANE*3]; /* Tx amplitude control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct xgene_phy_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) enum xgene_phy_mode mode; /* Mode of operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) enum clk_type_t clk_type; /* Input clock selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void __iomem *sds_base; /* PHY CSR base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct clk *clk; /* Optional clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Override Serdes parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct xgene_sata_override_param sata_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * For chip earlier than A3 version, enable this flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * To enable, pass boot argument phy_xgene.preA3Chip=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int preA3Chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) module_param_named(preA3Chip, preA3Chip, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 indirect_data_reg, u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned long deadline = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) cmd = CFG_IND_ADDR_SET(cmd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel(data, csr_base + indirect_data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) readl(csr_base + indirect_data_reg); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) writel(cmd, csr_base + indirect_cmd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) readl(csr_base + indirect_cmd_reg); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val = readl(csr_base + indirect_cmd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } while (!(val & CFG_IND_CMD_DONE_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) time_before(jiffies, deadline));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!(val & CFG_IND_CMD_DONE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) csr_base + indirect_cmd_reg, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static void sds_rd(void __iomem *csr_base, u32 indirect_cmd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 indirect_data_reg, u32 addr, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) unsigned long deadline = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cmd = CFG_IND_RD_CMD_MASK | CFG_IND_CMD_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) cmd = CFG_IND_ADDR_SET(cmd, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writel(cmd, csr_base + indirect_cmd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) readl(csr_base + indirect_cmd_reg); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val = readl(csr_base + indirect_cmd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) } while (!(val & CFG_IND_CMD_DONE_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) time_before(jiffies, deadline));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *data = readl(csr_base + indirect_data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!(val & CFG_IND_CMD_DONE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pr_err("SDS WR timeout at 0x%p offset 0x%08X value 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) csr_base + indirect_cmd_reg, addr, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void cmu_wr(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) void __iomem *sds_base = ctx->sds_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (cmu_type == REF_CMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) reg += SERDES_PLL_REF_INDIRECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) reg += SERDES_PLL_INDIRECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SATA_ENET_SDS_IND_WDATA_REG, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void cmu_rd(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 reg, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) void __iomem *sds_base = ctx->sds_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (cmu_type == REF_CMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reg += SERDES_PLL_REF_INDIRECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) reg += SERDES_PLL_INDIRECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) SATA_ENET_SDS_IND_RDATA_REG, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pr_debug("CMU RD addr 0x%X value 0x%08X\n", reg, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void cmu_toggle1to0(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) cmu_rd(ctx, cmu_type, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) cmu_wr(ctx, cmu_type, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) cmu_rd(ctx, cmu_type, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) val &= ~bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) cmu_wr(ctx, cmu_type, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void cmu_clrbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) cmu_rd(ctx, cmu_type, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val &= ~bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) cmu_wr(ctx, cmu_type, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void cmu_setbits(struct xgene_phy_ctx *ctx, enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 reg, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) cmu_rd(ctx, cmu_type, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cmu_wr(ctx, cmu_type, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void __iomem *sds_base = ctx->sds_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) reg += SERDES_INDIRECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) reg += lane * SERDES_LANE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sds_wr(sds_base, SATA_ENET_SDS_IND_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) SATA_ENET_SDS_IND_WDATA_REG, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) SATA_ENET_SDS_IND_RDATA_REG, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) void __iomem *sds_base = ctx->sds_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) reg += SERDES_INDIRECT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) reg += lane * SERDES_LANE_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) sds_rd(sds_base, SATA_ENET_SDS_IND_CMD_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) SATA_ENET_SDS_IND_RDATA_REG, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pr_debug("SERDES RD addr 0x%X value 0x%08X\n", reg, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) serdes_rd(ctx, lane, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) val &= ~bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) serdes_wr(ctx, lane, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) serdes_rd(ctx, lane, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) val |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) serdes_wr(ctx, lane, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void xgene_phy_cfg_cmu_clk_type(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum clk_type_t clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Set the reset sequence delay for TX ready assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) cmu_rd(ctx, cmu_type, CMU_REG12, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) val = CMU_REG12_STATE_DELAY9_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) cmu_wr(ctx, cmu_type, CMU_REG12, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Set the programmable stage delays between various enable stages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) cmu_wr(ctx, cmu_type, CMU_REG13, 0x0222);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) cmu_wr(ctx, cmu_type, CMU_REG14, 0x2225);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Configure clock type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (clk_type == CLK_EXT_DIFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Select external clock mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cmu_rd(ctx, cmu_type, CMU_REG0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) val = CMU_REG0_PLL_REF_SEL_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) cmu_wr(ctx, cmu_type, CMU_REG0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Select CMOS as reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cmu_rd(ctx, cmu_type, CMU_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) cmu_wr(ctx, cmu_type, CMU_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_dbg(ctx->dev, "Set external reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else if (clk_type == CLK_INT_DIFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Select internal clock mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cmu_rd(ctx, cmu_type, CMU_REG0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) val = CMU_REG0_PLL_REF_SEL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) cmu_wr(ctx, cmu_type, CMU_REG0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Select CMOS as reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) cmu_rd(ctx, cmu_type, CMU_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cmu_wr(ctx, cmu_type, CMU_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dev_dbg(ctx->dev, "Set internal reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) } else if (clk_type == CLK_INT_SING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * NOTE: This clock type is NOT support for controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * whose internal clock shared in the PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Select internal clock mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) cmu_rd(ctx, cmu_type, CMU_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) cmu_wr(ctx, cmu_type, CMU_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Select CML as reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) cmu_rd(ctx, cmu_type, CMU_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) val = CMU_REG1_REFCLK_CMOS_SEL_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) cmu_wr(ctx, cmu_type, CMU_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_dbg(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "Set internal single ended reference clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void xgene_phy_sata_cfg_cmu_core(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) enum clk_type_t clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int ref_100MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (cmu_type == REF_CMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Set VCO calibration voltage threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cmu_rd(ctx, cmu_type, CMU_REG34, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val = CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) val = CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(val, 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) val = CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) val = CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(val, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) cmu_wr(ctx, cmu_type, CMU_REG34, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Set the VCO calibration counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) cmu_rd(ctx, cmu_type, CMU_REG0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (cmu_type == REF_CMU || preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) val = CMU_REG0_CAL_COUNT_RESOL_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cmu_wr(ctx, cmu_type, CMU_REG0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Configure PLL for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cmu_rd(ctx, cmu_type, CMU_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) val = CMU_REG1_PLL_CP_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (cmu_type == REF_CMU || preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) val = CMU_REG1_PLL_CP_SEL_SET(val, 0x5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) val = CMU_REG1_PLL_CP_SEL_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (cmu_type == REF_CMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cmu_wr(ctx, cmu_type, CMU_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (cmu_type != REF_CMU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Configure the PLL for either 100MHz or 50MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cmu_rd(ctx, cmu_type, CMU_REG2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (cmu_type == REF_CMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) val = CMU_REG2_PLL_LFRES_SET(val, 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ref_100MHz = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val = CMU_REG2_PLL_LFRES_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (clk_type == CLK_EXT_DIFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ref_100MHz = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ref_100MHz = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (ref_100MHz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_100M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_100M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) val = CMU_REG2_PLL_FBDIV_SET(val, FBDIV_VAL_50M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) val = CMU_REG2_PLL_REFDIV_SET(val, REFDIV_VAL_50M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) cmu_wr(ctx, cmu_type, CMU_REG2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Configure the VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) cmu_rd(ctx, cmu_type, CMU_REG3, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (cmu_type == REF_CMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) val = CMU_REG3_VCOVARSEL_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val = CMU_REG3_VCOVARSEL_SET(val, 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) val = CMU_REG3_VCO_MOMSEL_INIT_SET(val, 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = CMU_REG3_VCO_MANMOMSEL_SET(val, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cmu_wr(ctx, cmu_type, CMU_REG3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Disable force PLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) cmu_rd(ctx, cmu_type, CMU_REG26, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) val = CMU_REG26_FORCE_PLL_LOCK_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) cmu_wr(ctx, cmu_type, CMU_REG26, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Setup PLL loop filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) cmu_rd(ctx, cmu_type, CMU_REG5, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val = CMU_REG5_PLL_LFSMCAP_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) val = CMU_REG5_PLL_LFCAP_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (cmu_type == REF_CMU || !preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) val = CMU_REG5_PLL_LOCK_RESOLUTION_SET(val, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) cmu_wr(ctx, cmu_type, CMU_REG5, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* Enable or disable manual calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) cmu_rd(ctx, cmu_type, CMU_REG6, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = CMU_REG6_PLL_VREGTRIM_SET(val, preA3Chip ? 0x0 : 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) val = CMU_REG6_MAN_PVT_CAL_SET(val, preA3Chip ? 0x1 : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) cmu_wr(ctx, cmu_type, CMU_REG6, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Configure lane for 20-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (cmu_type == PHY_CMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) cmu_rd(ctx, cmu_type, CMU_REG9, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val = CMU_REG9_TX_WORD_MODE_CH1_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) CMU_REG9_WORD_LEN_20BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) val = CMU_REG9_TX_WORD_MODE_CH0_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) CMU_REG9_WORD_LEN_20BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!preA3Chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) val = CMU_REG9_VBG_BYPASSB_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) val = CMU_REG9_IGEN_BYPASS_SET(val , 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) cmu_wr(ctx, cmu_type, CMU_REG9, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!preA3Chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) cmu_rd(ctx, cmu_type, CMU_REG10, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) val = CMU_REG10_VREG_REFSEL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cmu_wr(ctx, cmu_type, CMU_REG10, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) cmu_rd(ctx, cmu_type, CMU_REG16, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val = CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) val = CMU_REG16_BYPASS_PLL_LOCK_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (cmu_type == REF_CMU || preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) cmu_wr(ctx, cmu_type, CMU_REG16, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* Configure for SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) cmu_rd(ctx, cmu_type, CMU_REG30, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) val = CMU_REG30_PCIE_MODE_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) val = CMU_REG30_LOCK_COUNT_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) cmu_wr(ctx, cmu_type, CMU_REG30, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Disable state machine bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) cmu_wr(ctx, cmu_type, CMU_REG31, 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) cmu_rd(ctx, cmu_type, CMU_REG32, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) val = CMU_REG32_PVT_CAL_WAIT_SEL_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (cmu_type == REF_CMU || preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) val = CMU_REG32_IREF_ADJ_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) val = CMU_REG32_IREF_ADJ_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) cmu_wr(ctx, cmu_type, CMU_REG32, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Set VCO calibration threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (cmu_type != REF_CMU && preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cmu_wr(ctx, cmu_type, CMU_REG34, 0x8d27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) cmu_wr(ctx, cmu_type, CMU_REG34, 0x873c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* Set CTLE Override and override waiting from state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) cmu_wr(ctx, cmu_type, CMU_REG37, 0xF00F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void xgene_phy_ssc_enable(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) enum cmu_type_t cmu_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* Set SSC modulation value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) cmu_rd(ctx, cmu_type, CMU_REG35, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) val = CMU_REG35_PLL_SSC_MOD_SET(val, 98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) cmu_wr(ctx, cmu_type, CMU_REG35, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* Enable SSC, set vertical step and DSM value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) cmu_rd(ctx, cmu_type, CMU_REG36, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) val = CMU_REG36_PLL_SSC_VSTEP_SET(val, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = CMU_REG36_PLL_SSC_EN_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) val = CMU_REG36_PLL_SSC_DSMSEL_SET(val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) cmu_wr(ctx, cmu_type, CMU_REG36, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Reset the PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) cmu_clrbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Force VCO calibration to restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) cmu_toggle1to0(ctx, cmu_type, CMU_REG32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) CMU_REG32_FORCE_VCOCAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static void xgene_phy_sata_cfg_lanes(struct xgene_phy_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) for (lane = 0; lane < MAX_LANE; lane++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) serdes_wr(ctx, lane, RXTX_REG147, 0x6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Set boost control for quarter, half, and full rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) serdes_rd(ctx, lane, RXTX_REG0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) val = RXTX_REG0_CTLE_EQ_HR_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) val = RXTX_REG0_CTLE_EQ_QR_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) val = RXTX_REG0_CTLE_EQ_FR_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) serdes_wr(ctx, lane, RXTX_REG0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Set boost control value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) serdes_rd(ctx, lane, RXTX_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) val = RXTX_REG1_RXACVCM_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) val = RXTX_REG1_CTLE_EQ_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ctx->sata_param.txboostgain[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) serdes_wr(ctx, lane, RXTX_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Latch VTT value based on the termination to ground and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) enable TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) serdes_rd(ctx, lane, RXTX_REG2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) val = RXTX_REG2_VTT_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) val = RXTX_REG2_VTT_SEL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) val = RXTX_REG2_TX_FIFO_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) serdes_wr(ctx, lane, RXTX_REG2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Configure Tx for 20-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) serdes_rd(ctx, lane, RXTX_REG4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) val = RXTX_REG4_TX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) serdes_wr(ctx, lane, RXTX_REG4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!preA3Chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) serdes_rd(ctx, lane, RXTX_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) val = RXTX_REG1_RXVREG1_SET(val, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) val = RXTX_REG1_RXIREF_ADJ_SET(val, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) serdes_wr(ctx, lane, RXTX_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Set pre-emphasis first 1 and 2, and post-emphasis values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) serdes_rd(ctx, lane, RXTX_REG5, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) val = RXTX_REG5_TX_CN1_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ctx->sata_param.txprecursor_cn1[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) val = RXTX_REG5_TX_CP1_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ctx->sata_param.txpostcursor_cp1[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) val = RXTX_REG5_TX_CN2_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ctx->sata_param.txprecursor_cn2[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) serdes_wr(ctx, lane, RXTX_REG5, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Set TX amplitude value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) serdes_rd(ctx, lane, RXTX_REG6, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) val = RXTX_REG6_TXAMP_CNTL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ctx->sata_param.txamplitude[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) val = RXTX_REG6_TXAMP_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) val = RXTX_REG6_TX_IDLE_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) val = RXTX_REG6_RX_BIST_RESYNC_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) val = RXTX_REG6_RX_BIST_ERRCNT_RD_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) serdes_wr(ctx, lane, RXTX_REG6, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* Configure Rx for 20-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) serdes_rd(ctx, lane, RXTX_REG7, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) val = RXTX_REG7_BIST_ENA_RX_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) val = RXTX_REG7_RX_WORD_MODE_SET(val, CMU_REG9_WORD_LEN_20BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) serdes_wr(ctx, lane, RXTX_REG7, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Set CDR and LOS values and enable Rx SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) serdes_rd(ctx, lane, RXTX_REG8, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) val = RXTX_REG8_CDR_LOOP_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) val = RXTX_REG8_CDR_BYPASS_RXLOS_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) val = RXTX_REG8_SSC_ENABLE_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) val = RXTX_REG8_SD_DISABLE_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) val = RXTX_REG8_SD_VREF_SET(val, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) serdes_wr(ctx, lane, RXTX_REG8, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Set phase adjust upper/lower limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) serdes_rd(ctx, lane, RXTX_REG11, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) val = RXTX_REG11_PHASE_ADJUST_LIMIT_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) serdes_wr(ctx, lane, RXTX_REG11, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Enable Latch Off; disable SUMOS and Tx termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) serdes_rd(ctx, lane, RXTX_REG12, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) val = RXTX_REG12_LATCH_OFF_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) val = RXTX_REG12_SUMOS_ENABLE_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) serdes_wr(ctx, lane, RXTX_REG12, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Set period error latch to 512T and enable BWL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) serdes_rd(ctx, lane, RXTX_REG26, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) val = RXTX_REG26_PERIOD_ERROR_LATCH_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) val = RXTX_REG26_BLWC_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) serdes_wr(ctx, lane, RXTX_REG26, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) serdes_wr(ctx, lane, RXTX_REG28, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Set DFE loop preset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) serdes_wr(ctx, lane, RXTX_REG31, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* Set Eye Monitor counter width to 12-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) serdes_rd(ctx, lane, RXTX_REG61, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) val = RXTX_REG61_ISCAN_INBERT_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) val = RXTX_REG61_LOADFREQ_SHIFT_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) val = RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) serdes_wr(ctx, lane, RXTX_REG61, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) serdes_rd(ctx, lane, RXTX_REG62, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) val = RXTX_REG62_PERIOD_H1_QLATCH_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) serdes_wr(ctx, lane, RXTX_REG62, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Set BW select tap X for DFE loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) for (i = 0; i < 9; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) reg = RXTX_REG81 + i * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) serdes_rd(ctx, lane, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) val = RXTX_REG89_MU_TH7_SET(val, 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) val = RXTX_REG89_MU_TH8_SET(val, 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) val = RXTX_REG89_MU_TH9_SET(val, 0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) serdes_wr(ctx, lane, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Set BW select tap X for frequency adjust loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) reg = RXTX_REG96 + i * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) serdes_rd(ctx, lane, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) val = RXTX_REG96_MU_FREQ1_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) val = RXTX_REG96_MU_FREQ2_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) val = RXTX_REG96_MU_FREQ3_SET(val, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) serdes_wr(ctx, lane, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Set BW select tap X for phase adjust loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) reg = RXTX_REG99 + i * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) serdes_rd(ctx, lane, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) val = RXTX_REG99_MU_PHASE1_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) val = RXTX_REG99_MU_PHASE2_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) val = RXTX_REG99_MU_PHASE3_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) serdes_wr(ctx, lane, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) serdes_rd(ctx, lane, RXTX_REG102, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) val = RXTX_REG102_FREQLOOP_LIMIT_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) serdes_wr(ctx, lane, RXTX_REG102, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) serdes_wr(ctx, lane, RXTX_REG114, 0xffe0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) serdes_rd(ctx, lane, RXTX_REG125, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) val = RXTX_REG125_SIGN_PQ_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ctx->sata_param.txeyedirection[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) val = RXTX_REG125_PQ_REG_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ctx->sata_param.txeyetuning[lane * 3 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ctx->sata_param.speed[lane]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) val = RXTX_REG125_PHZ_MANUAL_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) serdes_wr(ctx, lane, RXTX_REG125, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) serdes_rd(ctx, lane, RXTX_REG127, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) serdes_wr(ctx, lane, RXTX_REG127, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) serdes_rd(ctx, lane, RXTX_REG128, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) val = RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) serdes_wr(ctx, lane, RXTX_REG128, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) serdes_rd(ctx, lane, RXTX_REG145, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) val = RXTX_REG145_RXDFE_CONFIG_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) val = RXTX_REG145_TX_IDLE_SATA_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (preA3Chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) val = RXTX_REG145_RXES_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) val = RXTX_REG145_RXES_ENA_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) val = RXTX_REG145_RXVWES_LATENA_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) serdes_wr(ctx, lane, RXTX_REG145, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * Set Rx LOS filter clock rate, sample rate, and threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) reg = RXTX_REG148 + i * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) serdes_wr(ctx, lane, reg, 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int xgene_phy_cal_rdy_chk(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) enum clk_type_t clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) void __iomem *csr_serdes = ctx->sds_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Release PHY main reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) writel(0xdf, csr_serdes + SATA_ENET_SDS_RST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) readl(csr_serdes + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (cmu_type != REF_CMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cmu_setbits(ctx, cmu_type, CMU_REG5, CMU_REG5_PLL_RESETB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * As per PHY design spec, the PLL reset requires a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * of 800us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) usleep_range(800, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) cmu_rd(ctx, cmu_type, CMU_REG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) val = CMU_REG1_PLL_MANUALCAL_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) cmu_wr(ctx, cmu_type, CMU_REG1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * As per PHY design spec, the PLL auto calibration requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * a minimum of 800us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) usleep_range(800, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) cmu_toggle1to0(ctx, cmu_type, CMU_REG32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) CMU_REG32_FORCE_VCOCAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * As per PHY design spec, the PLL requires a minimum of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * 800us to settle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) usleep_range(800, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (!preA3Chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) goto skip_manual_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * Configure the termination resister calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * The serial receive pins, RXP/RXN, have TERMination resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * that is required to be calibrated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) cmu_rd(ctx, cmu_type, CMU_REG17, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) val = CMU_REG17_RESERVED_7_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) cmu_wr(ctx, cmu_type, CMU_REG17, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) cmu_toggle1to0(ctx, cmu_type, CMU_REG17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) CMU_REG17_PVT_TERM_MAN_ENA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * resistors that are required to the calibrated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Configure the pull DOWN calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) cmu_rd(ctx, cmu_type, CMU_REG17, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) val = CMU_REG17_RESERVED_7_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) cmu_wr(ctx, cmu_type, CMU_REG17, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) cmu_toggle1to0(ctx, cmu_type, CMU_REG16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) CMU_REG16_PVT_DN_MAN_ENA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Configure the pull UP calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) cmu_rd(ctx, cmu_type, CMU_REG17, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) val = CMU_REG17_PVT_CODE_R2A_SET(val, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) val = CMU_REG17_RESERVED_7_SET(val, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cmu_wr(ctx, cmu_type, CMU_REG17, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) cmu_toggle1to0(ctx, cmu_type, CMU_REG16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) CMU_REG16_PVT_UP_MAN_ENA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) skip_manual_cal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* Poll the PLL calibration completion status for at least 1 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) loop = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) cmu_rd(ctx, cmu_type, CMU_REG7, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (CMU_REG7_PLL_CALIB_DONE_RD(val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * As per PHY design spec, PLL calibration status requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * a minimum of 10us to be updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) } while (--loop > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) cmu_rd(ctx, cmu_type, CMU_REG7, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_dbg(ctx->dev, "PLL calibration %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) CMU_REG7_PLL_CALIB_DONE_RD(val) ? "done" : "failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (CMU_REG7_VCO_CAL_FAIL_RD(val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "PLL calibration failed due to VCO failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_dbg(ctx->dev, "PLL calibration successful\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) cmu_rd(ctx, cmu_type, CMU_REG15, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static void xgene_phy_pdwn_force_vco(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) enum cmu_type_t cmu_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) enum clk_type_t clk_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dev_dbg(ctx->dev, "Reset VCO and re-start again\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (cmu_type == PHY_CMU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) cmu_rd(ctx, cmu_type, CMU_REG16, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) val = CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(val, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) cmu_wr(ctx, cmu_type, CMU_REG16, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) cmu_toggle1to0(ctx, cmu_type, CMU_REG0, CMU_REG0_PDOWN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) cmu_toggle1to0(ctx, cmu_type, CMU_REG32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) CMU_REG32_FORCE_VCOCAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static int xgene_phy_hw_init_sata(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) enum clk_type_t clk_type, int ssc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) void __iomem *sds_base = ctx->sds_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Configure the PHY for operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_dbg(ctx->dev, "Reset PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Place PHY into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) writel(0x0, sds_base + SATA_ENET_SDS_RST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) val = readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* Release PHY lane from reset (active high) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) writel(0x20, sds_base + SATA_ENET_SDS_RST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Release all PHY module out of reset except PHY main reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) writel(0xde, sds_base + SATA_ENET_SDS_RST_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) readl(sds_base + SATA_ENET_SDS_RST_CTL); /* Force a barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* Set the operation speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) val = readl(sds_base + SATA_ENET_SDS_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) val = CFG_I_SPD_SEL_CDR_OVR1_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ctx->sata_param.txspeed[ctx->sata_param.speed[0]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) writel(val, sds_base + SATA_ENET_SDS_CTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) val = readl(sds_base + SATA_ENET_SDS_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) val = REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(val, 0x4421);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) writel(val, sds_base + SATA_ENET_SDS_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Configure the clock macro unit (CMU) clock type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) xgene_phy_cfg_cmu_clk_type(ctx, PHY_CMU, clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* Configure the clock macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) xgene_phy_sata_cfg_cmu_core(ctx, PHY_CMU, clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Enable SSC if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (ssc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) xgene_phy_ssc_enable(ctx, PHY_CMU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* Configure PHY lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) xgene_phy_sata_cfg_lanes(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Set Rx/Tx 20-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) val = readl(sds_base + SATA_ENET_SDS_PCS_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) val = REGSPEC_CFG_I_RX_WORDMODE0_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) val = REGSPEC_CFG_I_TX_WORDMODE0_SET(val, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) writel(val, sds_base + SATA_ENET_SDS_PCS_CTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Start PLL calibration and try for three times */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) i = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (!xgene_phy_cal_rdy_chk(ctx, PHY_CMU, clk_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) /* If failed, toggle the VCO power signal and start again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) } while (--i > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Even on failure, allow to continue any way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (i <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_err(ctx->dev, "PLL calibration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int xgene_phy_hw_initialize(struct xgene_phy_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) enum clk_type_t clk_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int ssc_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (ctx->mode == MODE_SATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) rc = xgene_phy_hw_init_sata(ctx, clk_type, ssc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) dev_err(ctx->dev, "Un-supported customer pin mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ctx->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * Receiver Offset Calibration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * Calibrate the receiver signal path offset in two steps - summar and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * latch calibrations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) } serdes_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {RXTX_REG38, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {RXTX_REG39, 0xff00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {RXTX_REG40, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {RXTX_REG41, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {RXTX_REG42, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {RXTX_REG43, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {RXTX_REG44, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {RXTX_REG45, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {RXTX_REG46, 0xffff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {RXTX_REG47, 0xfffc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {RXTX_REG48, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {RXTX_REG49, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {RXTX_REG50, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {RXTX_REG51, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {RXTX_REG52, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {RXTX_REG53, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) {RXTX_REG54, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {RXTX_REG55, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Start SUMMER calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) serdes_setbits(ctx, lane, RXTX_REG127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) RXTX_REG127_FORCE_SUM_CAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * As per PHY design spec, the Summer calibration requires a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * of 100us to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) usleep_range(100, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) serdes_clrbits(ctx, lane, RXTX_REG127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) RXTX_REG127_FORCE_SUM_CAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) * As per PHY design spec, the auto calibration requires a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) * of 100us to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) usleep_range(100, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Start latch calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) serdes_setbits(ctx, lane, RXTX_REG127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) RXTX_REG127_FORCE_LAT_CAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * As per PHY design spec, the latch calibration requires a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * of 100us to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) usleep_range(100, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) serdes_clrbits(ctx, lane, RXTX_REG127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) RXTX_REG127_FORCE_LAT_CAL_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* Configure the PHY lane for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) serdes_wr(ctx, lane, RXTX_REG28, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) serdes_clrbits(ctx, lane, RXTX_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) serdes_clrbits(ctx, lane, RXTX_REG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) for (i = 0; i < ARRAY_SIZE(serdes_reg); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) serdes_wr(ctx, lane, serdes_reg[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) serdes_reg[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Reset digital Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* As per PHY design spec, the reset requires a minimum of 100us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static int xgene_phy_get_avg(int accum, int samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return (accum + (samples / 2)) / samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) int max_loop = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) int avg_loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) int lat_do = 0, lat_xo = 0, lat_eo = 0, lat_so = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) int lat_de = 0, lat_xe = 0, lat_ee = 0, lat_se = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) int sum_cal = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) int lat_do_itr, lat_xo_itr, lat_eo_itr, lat_so_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) int lat_de_itr, lat_xe_itr, lat_ee_itr, lat_se_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) int sum_cal_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int fail_even;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int fail_odd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Enable RX Hi-Z termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) serdes_setbits(ctx, lane, RXTX_REG12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) RXTX_REG12_RX_DET_TERM_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* Turn off DFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) serdes_wr(ctx, lane, RXTX_REG28, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* DFE Presets to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) serdes_wr(ctx, lane, RXTX_REG31, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * Receiver Offset Calibration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * Calibrate the receiver signal path offset in two steps - summar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * and latch calibration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Runs the "Receiver Offset Calibration multiple times to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * the average value to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) while (avg_loop < max_loop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* Start the calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) xgene_phy_force_lat_summer_cal(ctx, lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) serdes_rd(ctx, lane, RXTX_REG21, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) lat_do_itr = RXTX_REG21_DO_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) lat_xo_itr = RXTX_REG21_XO_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) fail_odd = RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) serdes_rd(ctx, lane, RXTX_REG22, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) lat_eo_itr = RXTX_REG22_EO_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) lat_so_itr = RXTX_REG22_SO_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) fail_even = RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) serdes_rd(ctx, lane, RXTX_REG23, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) lat_de_itr = RXTX_REG23_DE_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) lat_xe_itr = RXTX_REG23_XE_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) serdes_rd(ctx, lane, RXTX_REG24, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) lat_ee_itr = RXTX_REG24_EE_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) lat_se_itr = RXTX_REG24_SE_LATCH_CALOUT_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) serdes_rd(ctx, lane, RXTX_REG121, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) sum_cal_itr = RXTX_REG121_SUMOS_CAL_CODE_RD(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* Check for failure. If passed, sum them for averaging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if ((fail_even == 0 || fail_even == 1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) (fail_odd == 0 || fail_odd == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) lat_do += lat_do_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) lat_xo += lat_xo_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) lat_eo += lat_eo_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) lat_so += lat_so_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) lat_de += lat_de_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) lat_xe += lat_xe_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) lat_ee += lat_ee_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) lat_se += lat_se_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) sum_cal += sum_cal_itr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) lat_do_itr, lat_xo_itr, lat_eo_itr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) lat_so_itr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) lat_de_itr, lat_xe_itr, lat_ee_itr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) lat_se_itr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ++avg_loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) "Receiver calibration failed at %d loop\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) avg_loop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) xgene_phy_reset_rxd(ctx, lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* Update latch manual calibration with average value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) serdes_rd(ctx, lane, RXTX_REG127, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) val = RXTX_REG127_DO_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) xgene_phy_get_avg(lat_do, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) val = RXTX_REG127_XO_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) xgene_phy_get_avg(lat_xo, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) serdes_wr(ctx, lane, RXTX_REG127, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) serdes_rd(ctx, lane, RXTX_REG128, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) val = RXTX_REG128_EO_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) xgene_phy_get_avg(lat_eo, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) val = RXTX_REG128_SO_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) xgene_phy_get_avg(lat_so, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) serdes_wr(ctx, lane, RXTX_REG128, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) serdes_rd(ctx, lane, RXTX_REG129, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) val = RXTX_REG129_DE_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) xgene_phy_get_avg(lat_de, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) val = RXTX_REG129_XE_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) xgene_phy_get_avg(lat_xe, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) serdes_wr(ctx, lane, RXTX_REG129, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) serdes_rd(ctx, lane, RXTX_REG130, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) val = RXTX_REG130_EE_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) xgene_phy_get_avg(lat_ee, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) val = RXTX_REG130_SE_LATCH_MANCAL_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) xgene_phy_get_avg(lat_se, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) serdes_wr(ctx, lane, RXTX_REG130, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* Update SUMMER calibration with average value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) serdes_rd(ctx, lane, RXTX_REG14, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) val = RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) xgene_phy_get_avg(sum_cal, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) serdes_wr(ctx, lane, RXTX_REG14, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) dev_dbg(ctx->dev, "Average Value:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) xgene_phy_get_avg(lat_do, max_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) xgene_phy_get_avg(lat_xo, max_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) xgene_phy_get_avg(lat_eo, max_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) xgene_phy_get_avg(lat_so, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) xgene_phy_get_avg(lat_de, max_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) xgene_phy_get_avg(lat_xe, max_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) xgene_phy_get_avg(lat_ee, max_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) xgene_phy_get_avg(lat_se, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev_dbg(ctx->dev, "SUM 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) xgene_phy_get_avg(sum_cal, max_loop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) serdes_rd(ctx, lane, RXTX_REG14, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) val = RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) serdes_wr(ctx, lane, RXTX_REG14, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_dbg(ctx->dev, "Enable Manual Summer calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) serdes_rd(ctx, lane, RXTX_REG127, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) val = RXTX_REG127_LATCH_MAN_CAL_ENA_SET(val, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) dev_dbg(ctx->dev, "Enable Manual Latch calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) serdes_wr(ctx, lane, RXTX_REG127, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* Disable RX Hi-Z termination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) serdes_rd(ctx, lane, RXTX_REG12, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) val = RXTX_REG12_RX_DET_TERM_ENABLE_SET(val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) serdes_wr(ctx, lane, RXTX_REG12, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* Turn on DFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) serdes_wr(ctx, lane, RXTX_REG28, 0x0007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* Set DFE preset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) serdes_wr(ctx, lane, RXTX_REG31, 0x7e00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static int xgene_phy_hw_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct xgene_phy_ctx *ctx = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) rc = xgene_phy_hw_initialize(ctx, CLK_EXT_DIFF, SSC_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dev_err(ctx->dev, "PHY initialize failed %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* Setup clock properly after PHY configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (!IS_ERR(ctx->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* HW requires an toggle of the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) clk_prepare_enable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) clk_disable_unprepare(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) clk_prepare_enable(ctx->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* Compute average value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) for (i = 0; i < MAX_LANE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) xgene_phy_gen_avg_val(ctx, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) dev_dbg(ctx->dev, "PHY initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const struct phy_ops xgene_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .init = xgene_phy_hw_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static struct phy *xgene_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct xgene_phy_ctx *ctx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (args->args_count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (args->args[0] >= MODE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ctx->mode = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) return ctx->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static void xgene_phy_get_param(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) const char *name, u32 *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) int count, u32 *default_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) u32 conv_factor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) buffer[i] /= conv_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* Does not exist, load default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) buffer[i] = default_val[i % 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int xgene_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct xgene_phy_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) u32 default_spd[] = DEFAULT_SATA_SPD_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) u32 default_txboost_gain[] = DEFAULT_SATA_TXBOOST_GAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) u32 default_txeye_direction[] = DEFAULT_SATA_TXEYEDIRECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) u32 default_txeye_tuning[] = DEFAULT_SATA_TXEYETUNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u32 default_txamp[] = DEFAULT_SATA_TXAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) u32 default_txcn1[] = DEFAULT_SATA_TXCN1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 default_txcn2[] = DEFAULT_SATA_TXCN2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u32 default_txcp1[] = DEFAULT_SATA_TXCP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ctx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ctx->sds_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (IS_ERR(ctx->sds_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return PTR_ERR(ctx->sds_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* Retrieve optional clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ctx->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* Load override paramaters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) xgene_phy_get_param(pdev, "apm,tx-eye-tuning",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) xgene_phy_get_param(pdev, "apm,tx-eye-direction",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) xgene_phy_get_param(pdev, "apm,tx-boost-gain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ctx->sata_param.txboostgain, 6, default_txboost_gain, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) xgene_phy_get_param(pdev, "apm,tx-amplitude",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ctx->sata_param.txamplitude, 6, default_txamp, 13300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) xgene_phy_get_param(pdev, "apm,tx-pre-cursor1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) xgene_phy_get_param(pdev, "apm,tx-pre-cursor2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) xgene_phy_get_param(pdev, "apm,tx-post-cursor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) xgene_phy_get_param(pdev, "apm,tx-speed",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ctx->sata_param.txspeed, 3, default_spd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) for (i = 0; i < MAX_LANE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ctx->sata_param.speed[i] = 2; /* Default to Gen3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (IS_ERR(ctx->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) dev_dbg(&pdev->dev, "Failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return PTR_ERR(ctx->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) phy_set_drvdata(ctx->phy, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static const struct of_device_id xgene_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {.compatible = "apm,xgene-phy",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) MODULE_DEVICE_TABLE(of, xgene_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static struct platform_driver xgene_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .probe = xgene_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .name = "xgene-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .of_match_table = xgene_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) module_platform_driver(xgene_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) MODULE_AUTHOR("Loc Ho <lho@apm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) MODULE_VERSION("0.1");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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