^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMG Pistachio USB PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/phy/phy-pistachio-usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB_PHY_CONTROL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB_PHY_CONTROL1_FSEL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USB_PHY_CONTROL1_FSEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USB_PHY_STRAP_CONTROL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USB_PHY_STRAP_CONTROL_REFCLK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USB_PHY_STRAP_CONTROL_REFCLK_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USB_PHY_STATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USB_PHY_STATUS_RX_PHY_CLK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USB_PHY_STATUS_RX_UTMI_CLK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USB_PHY_STATUS_VBUS_FAULT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pistachio_usb_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regmap *cr_top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const unsigned long fsel_rate_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 9600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 19200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int pistachio_usb_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long timeout, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ret = clk_prepare_enable(p_phy->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) USB_PHY_STRAP_CONTROL_REFCLK_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) USB_PHY_STRAP_CONTROL_REFCLK_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rate = clk_get_rate(p_phy->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (i = 0; i < ARRAY_SIZE(fsel_rate_map); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (rate == fsel_rate_map[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (i == ARRAY_SIZE(fsel_rate_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(p_phy->dev, "Unsupported clock rate: %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regmap_update_bits(p_phy->cr_top, USB_PHY_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) USB_PHY_CONTROL1_FSEL_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) USB_PHY_CONTROL1_FSEL_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) i << USB_PHY_CONTROL1_FSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) timeout = jiffies + msecs_to_jiffies(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (val & USB_PHY_STATUS_VBUS_FAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(p_phy->dev, "VBUS fault detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if ((val & USB_PHY_STATUS_RX_PHY_CLK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (val & USB_PHY_STATUS_RX_UTMI_CLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_disable_unprepare(p_phy->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int pistachio_usb_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_disable_unprepare(p_phy->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct phy_ops pistachio_usb_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .power_on = pistachio_usb_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .power_off = pistachio_usb_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int pistachio_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pistachio_usb_phy *p_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!p_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) p_phy->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) platform_set_drvdata(pdev, p_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) p_phy->cr_top = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "img,cr-top");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (IS_ERR(p_phy->cr_top)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_err(p_phy->dev, "Failed to get CR_TOP registers: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PTR_ERR(p_phy->cr_top));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PTR_ERR(p_phy->cr_top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) p_phy->phy_clk = devm_clk_get(p_phy->dev, "usb_phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (IS_ERR(p_phy->phy_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(p_phy->dev, "Failed to get usb_phy clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PTR_ERR(p_phy->phy_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return PTR_ERR(p_phy->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &p_phy->refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(p_phy->dev, "No reference clock selector specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) phy = devm_phy_create(p_phy->dev, NULL, &pistachio_usb_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(p_phy->dev, "Failed to create PHY: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PTR_ERR(phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) phy_set_drvdata(phy, p_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) provider = devm_of_phy_provider_register(p_phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(p_phy->dev, "Failed to register PHY provider: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PTR_ERR(provider));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct of_device_id pistachio_usb_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .compatible = "img,pistachio-usb-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(of, pistachio_usb_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct platform_driver pistachio_usb_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .probe = pistachio_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .name = "pistachio-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .of_match_table = pistachio_usb_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) module_platform_driver(pistachio_usb_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_DESCRIPTION("IMG Pistachio USB2.0 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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