^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PHY driver for NXP LPC18xx/43xx internal USB OTG PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* USB OTG PHY register offset and bit in CREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LPC18XX_CREG_CREG0 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPC18XX_CREG_CREG0_USB0PHY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct lpc18xx_usb_otg_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int lpc18xx_usb_otg_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The PHY must be clocked at 480 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ret = clk_set_rate(lpc->clk, 480000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return clk_prepare(lpc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int lpc18xx_usb_otg_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clk_unprepare(lpc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int lpc18xx_usb_otg_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ret = clk_enable(lpc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* The bit in CREG is cleared to enable the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ret = regmap_update_bits(lpc->reg, LPC18XX_CREG_CREG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) LPC18XX_CREG_CREG0_USB0PHY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) clk_disable(lpc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int lpc18xx_usb_otg_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = regmap_update_bits(lpc->reg, LPC18XX_CREG_CREG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) LPC18XX_CREG_CREG0_USB0PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) LPC18XX_CREG_CREG0_USB0PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_disable(lpc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct phy_ops lpc18xx_usb_otg_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .init = lpc18xx_usb_otg_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .exit = lpc18xx_usb_otg_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .power_on = lpc18xx_usb_otg_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .power_off = lpc18xx_usb_otg_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int lpc18xx_usb_otg_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct lpc18xx_usb_otg_phy *lpc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) lpc = devm_kzalloc(&pdev->dev, sizeof(*lpc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!lpc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) lpc->reg = syscon_node_to_regmap(pdev->dev.of_node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ERR(lpc->reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_err(&pdev->dev, "failed to get syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return PTR_ERR(lpc->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) lpc->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (IS_ERR(lpc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_err(&pdev->dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return PTR_ERR(lpc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) lpc->phy = devm_phy_create(&pdev->dev, NULL, &lpc18xx_usb_otg_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (IS_ERR(lpc->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_err(&pdev->dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return PTR_ERR(lpc->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) phy_set_drvdata(lpc->phy, lpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) phy_provider = devm_of_phy_provider_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct of_device_id lpc18xx_usb_otg_phy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .compatible = "nxp,lpc1850-usb-otg-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MODULE_DEVICE_TABLE(of, lpc18xx_usb_otg_phy_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct platform_driver lpc18xx_usb_otg_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .probe = lpc18xx_usb_otg_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "lpc18xx-usb-otg-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .of_match_table = lpc18xx_usb_otg_phy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) module_platform_driver(lpc18xx_usb_otg_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_DESCRIPTION("NXP LPC18xx/43xx USB OTG PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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