^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel LGM USB PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/usb/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CTRL1_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SRAM_EXT_LD_DONE BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SRAM_INIT_DONE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TCPC_OFFSET 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TCPC_MUX_CTL GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MUX_NC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MUX_USB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MUX_DP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MUX_USBDP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TCPC_FLIPPED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TCPC_LOW_POWER_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TCPC_VALID BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TCPC_CONN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (TCPC_VALID | FIELD_PREP(TCPC_MUX_CTL, MUX_USB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TCPC_DISCONN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) (TCPC_VALID | FIELD_PREP(TCPC_MUX_CTL, MUX_NC) | TCPC_LOW_POWER_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const char *const PHY_RESETS[] = { "phy31", "phy", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char *const CTL_RESETS[] = { "apb", "ctrl", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct tca_apb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct reset_control *resets[ARRAY_SIZE(PHY_RESETS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct work_struct wk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct usb_phy phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool regulator_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool phy_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int get_flipped(struct tca_apb *ta, bool *flipped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) union extcon_property_value property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = extcon_get_property(ta->phy.edev, EXTCON_USB_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXTCON_PROP_USB_TYPEC_POLARITY, &property);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_err(ta->phy.dev, "no polarity property from extcon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *flipped = property.intval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int phy_init(struct usb_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct tca_apb *ta = container_of(phy, struct tca_apb, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *ctrl1 = phy->io_priv + CTRL1_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int val, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ta->phy_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < ARRAY_SIZE(PHY_RESETS); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reset_control_deassert(ta->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = readl_poll_timeout(ctrl1, val, val & SRAM_INIT_DONE, 10, 10 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_err(ta->phy.dev, "SRAM init failed, 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(readl(ctrl1) | SRAM_EXT_LD_DONE, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ta->phy_initialized = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!ta->phy.edev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(TCPC_CONN, ta->phy.io_priv + TCPC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return phy->set_vbus(phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) schedule_work(&ta->wk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void phy_shutdown(struct usb_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct tca_apb *ta = container_of(phy, struct tca_apb, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!ta->phy_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ta->phy_initialized = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) flush_work(&ta->wk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ta->phy.set_vbus(&ta->phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ta->connected = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(TCPC_DISCONN, ta->phy.io_priv + TCPC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) for (i = 0; i < ARRAY_SIZE(PHY_RESETS); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reset_control_assert(ta->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int phy_set_vbus(struct usb_phy *phy, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct tca_apb *ta = container_of(phy, struct tca_apb, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!!on == ta->regulator_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = regulator_enable(ta->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = regulator_disable(ta->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ta->regulator_enabled = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_dbg(ta->phy.dev, "set vbus: %d\n", on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void tca_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct tca_apb *ta = container_of(work, struct tca_apb, wk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bool connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool flipped = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = get_flipped(ta, &flipped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) connected = extcon_get_state(ta->phy.edev, EXTCON_USB_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (connected == ta->connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ta->connected = connected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (connected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = TCPC_CONN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (flipped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val |= TCPC_FLIPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_dbg(ta->phy.dev, "connected%s\n", flipped ? " flipped" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val = TCPC_DISCONN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_dbg(ta->phy.dev, "disconnected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) writel(val, ta->phy.io_priv + TCPC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = ta->phy.set_vbus(&ta->phy, connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(ta->phy.dev, "failed to set VBUS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int id_notifier(struct notifier_block *nb, unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct tca_apb *ta = container_of(nb, struct tca_apb, phy.id_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ta->phy_initialized)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) schedule_work(&ta->wk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int vbus_notifier(struct notifier_block *nb, unsigned long evnt, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct reset_control *resets[ARRAY_SIZE(CTL_RESETS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct usb_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct tca_apb *ta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ta = devm_kzalloc(dev, sizeof(*ta), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!ta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) platform_set_drvdata(pdev, ta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) INIT_WORK(&ta->wk, tca_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) phy = &ta->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) phy->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) phy->type = USB_PHY_TYPE_USB3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) phy->init = phy_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) phy->shutdown = phy_shutdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) phy->set_vbus = phy_set_vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) phy->id_nb.notifier_call = id_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) phy->vbus_nb.notifier_call = vbus_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) phy->io_priv = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (IS_ERR(phy->io_priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PTR_ERR(phy->io_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ta->vbus = devm_regulator_get(dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (IS_ERR(ta->vbus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return PTR_ERR(ta->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) for (i = 0; i < ARRAY_SIZE(CTL_RESETS); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) resets[i] = devm_reset_control_get_exclusive(dev, CTL_RESETS[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (IS_ERR(resets[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(dev, "%s reset not found\n", CTL_RESETS[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return PTR_ERR(resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (i = 0; i < ARRAY_SIZE(PHY_RESETS); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ta->resets[i] = devm_reset_control_get_exclusive(dev, PHY_RESETS[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_ERR(ta->resets[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(dev, "%s reset not found\n", PHY_RESETS[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PTR_ERR(ta->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i < ARRAY_SIZE(CTL_RESETS); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) reset_control_assert(resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 0; i < ARRAY_SIZE(PHY_RESETS); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reset_control_assert(ta->resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * Out-of-band reset of the controller after PHY reset will cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * controller malfunctioning, so we should use in-band controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * reset only and leave the controller de-asserted here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < ARRAY_SIZE(CTL_RESETS); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reset_control_deassert(resets[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Need to wait at least 20us after de-assert the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) usleep_range(20, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return usb_add_phy_dev(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tca_apb *ta = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) usb_remove_phy(&ta->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct of_device_id intel_usb_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .compatible = "intel,lgm-usb-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_DEVICE_TABLE(of, intel_usb_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct platform_driver lgm_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "lgm-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .of_match_table = intel_usb_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .probe = phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .remove = phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) module_platform_driver(lgm_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DESCRIPTION("Intel LGM USB PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_AUTHOR("Li Yin <yin1.li@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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