^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SerDes PHY driver for Microsemi Ocelot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Microsemi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <soc/mscc/ocelot_hsio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/phy/phy-ocelot-serdes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct serdes_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct regmap *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct phy *phys[SERDES_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct serdes_macro {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Not used when in QSGMII or PCIe mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct serdes_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCB_S6G_CFG_TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int __serdes_write_mcb_s6g(struct regmap *regmap, u8 macro, u32 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) regmap_write(regmap, HSIO_MCB_S6G_ADDR_CFG, op |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HSIO_MCB_S6G_ADDR_CFG_SERDES6G_ADDR(BIT(macro)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return regmap_read_poll_timeout(regmap, HSIO_MCB_S6G_ADDR_CFG, regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (regval & op) != op, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MCB_S6G_CFG_TIMEOUT * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int serdes_commit_mcb_s6g(struct regmap *regmap, u8 macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return __serdes_write_mcb_s6g(regmap, macro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) HSIO_MCB_S6G_ADDR_CFG_SERDES6G_WR_ONE_SHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int serdes_update_mcb_s6g(struct regmap *regmap, u8 macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return __serdes_write_mcb_s6g(regmap, macro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) HSIO_MCB_S6G_ADDR_CFG_SERDES6G_RD_ONE_SHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 pll_fsm_ctrl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 ob_ena1v_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 des_bw_ana;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 ob_ena_cas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 if_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 ob_lev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 qrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (mode == PHY_INTERFACE_MODE_QSGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pll_fsm_ctrl_data = 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ob_ena1v_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ob_ena_cas = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) des_bw_ana = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ob_lev = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if_mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) qrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pll_fsm_ctrl_data = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ob_ena1v_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ob_ena_cas = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) des_bw_ana = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ob_lev = 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) qrate = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = serdes_update_mcb_s6g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Test pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) HSIO_S6G_COMMON_CFG_SYS_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) HSIO_S6G_PLL_CFG_PLL_FSM_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) HSIO_S6G_IB_CFG_IB_SIG_DET_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) HSIO_S6G_IB_CFG_IB_REG_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) HSIO_S6G_IB_CFG_IB_SAM_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) HSIO_S6G_IB_CFG_IB_EQZ_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) HSIO_S6G_IB_CFG_IB_CONCUR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) HSIO_S6G_IB_CFG_IB_CAL_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) HSIO_S6G_IB_CFG_IB_SIG_DET_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) HSIO_S6G_IB_CFG_IB_REG_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) HSIO_S6G_IB_CFG_IB_SAM_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) HSIO_S6G_IB_CFG_IB_EQZ_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) HSIO_S6G_IB_CFG_IB_CONCUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) HSIO_S6G_IB_CFG1_IB_FRC_OFFSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) HSIO_S6G_IB_CFG1_IB_FRC_LP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) HSIO_S6G_IB_CFG1_IB_FRC_MID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) HSIO_S6G_IB_CFG1_IB_FRC_HP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) HSIO_S6G_IB_CFG1_IB_FILT_OFFSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) HSIO_S6G_IB_CFG1_IB_FILT_LP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) HSIO_S6G_IB_CFG1_IB_FILT_MID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) HSIO_S6G_IB_CFG1_IB_FILT_HP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) HSIO_S6G_IB_CFG1_IB_FILT_OFFSET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) HSIO_S6G_IB_CFG1_IB_FILT_HP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) HSIO_S6G_IB_CFG1_IB_FILT_LP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) HSIO_S6G_IB_CFG1_IB_FILT_MID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_update_bits(regmap, HSIO_S6G_IB_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) HSIO_S6G_IB_CFG2_IB_UREG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) HSIO_S6G_IB_CFG2_IB_UREG(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regmap_update_bits(regmap, HSIO_S6G_IB_CFG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) HSIO_S6G_IB_CFG3_IB_INI_OFFSET_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) HSIO_S6G_IB_CFG3_IB_INI_LP_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) HSIO_S6G_IB_CFG3_IB_INI_MID_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) HSIO_S6G_IB_CFG3_IB_INI_HP_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) HSIO_S6G_IB_CFG3_IB_INI_OFFSET(31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) HSIO_S6G_IB_CFG3_IB_INI_LP(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) HSIO_S6G_IB_CFG3_IB_INI_MID(31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) HSIO_S6G_IB_CFG3_IB_INI_HP(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) HSIO_S6G_MISC_CFG_LANE_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) HSIO_S6G_MISC_CFG_LANE_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = serdes_commit_mcb_s6g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* OB + DES + IB + SER CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) regmap_update_bits(regmap, HSIO_S6G_OB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) HSIO_S6G_OB_CFG_OB_IDLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) HSIO_S6G_OB_CFG_OB_ENA1V_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) HSIO_S6G_OB_CFG_OB_POST0_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) HSIO_S6G_OB_CFG_OB_PREC_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) (ob_ena1v_mode ? HSIO_S6G_OB_CFG_OB_ENA1V_MODE : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) HSIO_S6G_OB_CFG_OB_POST0(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) HSIO_S6G_OB_CFG_OB_PREC(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_update_bits(regmap, HSIO_S6G_OB_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) HSIO_S6G_OB_CFG1_OB_ENA_CAS_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) HSIO_S6G_OB_CFG1_OB_LEV_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) HSIO_S6G_OB_CFG1_OB_LEV(ob_lev) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) HSIO_S6G_OB_CFG1_OB_ENA_CAS(ob_ena_cas));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) regmap_update_bits(regmap, HSIO_S6G_DES_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) HSIO_S6G_DES_CFG_DES_PHS_CTRL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) HSIO_S6G_DES_CFG_DES_CPMD_SEL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) HSIO_S6G_DES_CFG_DES_BW_ANA_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) HSIO_S6G_DES_CFG_DES_PHS_CTRL(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) HSIO_S6G_DES_CFG_DES_CPMD_SEL(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HSIO_S6G_DES_CFG_DES_BW_ANA(des_bw_ana));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) HSIO_S6G_IB_CFG1_IB_TSDET_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) HSIO_S6G_IB_CFG1_IB_TSDET(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regmap_update_bits(regmap, HSIO_S6G_SER_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) HSIO_S6G_SER_CFG_SER_ALISEL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) HSIO_S6G_SER_CFG_SER_ENALI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) HSIO_S6G_SER_CFG_SER_ALISEL(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) HSIO_S6G_PLL_CFG_PLL_DIV4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) HSIO_S6G_PLL_CFG_PLL_ENA_ROT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) HSIO_S6G_PLL_CFG_PLL_ROT_DIR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) HSIO_S6G_PLL_CFG_PLL_ROT_FRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) HSIO_S6G_PLL_CFG_PLL_FSM_CTRL_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) (pll_fsm_ctrl_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) regmap_update_bits(regmap, HSIO_S6G_COMMON_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) HSIO_S6G_COMMON_CFG_SYS_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) HSIO_S6G_COMMON_CFG_ENA_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) HSIO_S6G_COMMON_CFG_PWD_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) HSIO_S6G_COMMON_CFG_PWD_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) HSIO_S6G_COMMON_CFG_HRATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) HSIO_S6G_COMMON_CFG_QRATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) HSIO_S6G_COMMON_CFG_ENA_ELOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) HSIO_S6G_COMMON_CFG_ENA_FLOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) HSIO_S6G_COMMON_CFG_IF_MODE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) HSIO_S6G_COMMON_CFG_SYS_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) HSIO_S6G_COMMON_CFG_ENA_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (qrate ? HSIO_S6G_COMMON_CFG_QRATE : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) HSIO_S6G_COMMON_CFG_IF_MODE(if_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) HSIO_S6G_MISC_CFG_LANE_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) HSIO_S6G_MISC_CFG_DES_100FX_CPMD_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) HSIO_S6G_MISC_CFG_TX_LPI_MODE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) HSIO_S6G_MISC_CFG_LANE_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) HSIO_S6G_MISC_CFG_RX_LPI_MODE_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = serdes_commit_mcb_s6g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) regmap_update_bits(regmap, HSIO_S6G_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) HSIO_S6G_PLL_CFG_PLL_FSM_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) HSIO_S6G_PLL_CFG_PLL_FSM_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = serdes_commit_mcb_s6g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Wait for PLL bringup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) HSIO_S6G_IB_CFG_IB_CAL_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) HSIO_S6G_IB_CFG_IB_CAL_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) regmap_update_bits(regmap, HSIO_S6G_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) HSIO_S6G_MISC_CFG_LANE_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = serdes_commit_mcb_s6g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Wait for calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) msleep(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) regmap_update_bits(regmap, HSIO_S6G_IB_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) HSIO_S6G_IB_CFG_IB_REG_PAT_SEL_OFFSET(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) HSIO_S6G_IB_CFG_IB_SIG_DET_CLK_SEL(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) regmap_update_bits(regmap, HSIO_S6G_IB_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) HSIO_S6G_IB_CFG1_IB_TSDET_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) HSIO_S6G_IB_CFG1_IB_TSDET(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* IB CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MCB_S1G_CFG_TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int __serdes_write_mcb_s1g(struct regmap *regmap, u8 macro, u32 op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) regmap_write(regmap, HSIO_MCB_S1G_ADDR_CFG, op |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) HSIO_MCB_S1G_ADDR_CFG_SERDES1G_ADDR(BIT(macro)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return regmap_read_poll_timeout(regmap, HSIO_MCB_S1G_ADDR_CFG, regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) (regval & op) != op, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MCB_S1G_CFG_TIMEOUT * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int serdes_commit_mcb_s1g(struct regmap *regmap, u8 macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return __serdes_write_mcb_s1g(regmap, macro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) HSIO_MCB_S1G_ADDR_CFG_SERDES1G_WR_ONE_SHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int serdes_update_mcb_s1g(struct regmap *regmap, u8 macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return __serdes_write_mcb_s1g(regmap, macro,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) HSIO_MCB_S1G_ADDR_CFG_SERDES1G_RD_ONE_SHOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int serdes_init_s1g(struct regmap *regmap, u8 serdes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = serdes_update_mcb_s1g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) HSIO_S1G_COMMON_CFG_SYS_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) HSIO_S1G_COMMON_CFG_ENA_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) HSIO_S1G_COMMON_CFG_ENA_ELOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) HSIO_S1G_COMMON_CFG_ENA_FLOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) HSIO_S1G_COMMON_CFG_ENA_LANE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regmap_update_bits(regmap, HSIO_S1G_PLL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) HSIO_S1G_PLL_CFG_PLL_FSM_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) HSIO_S1G_PLL_CFG_PLL_FSM_CTRL_DATA(200) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) HSIO_S1G_PLL_CFG_PLL_FSM_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) HSIO_S1G_MISC_CFG_DES_100FX_CPMD_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) HSIO_S1G_MISC_CFG_LANE_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) HSIO_S1G_MISC_CFG_LANE_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = serdes_commit_mcb_s1g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_update_bits(regmap, HSIO_S1G_COMMON_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) HSIO_S1G_COMMON_CFG_SYS_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) HSIO_S1G_COMMON_CFG_SYS_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) regmap_update_bits(regmap, HSIO_S1G_MISC_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) HSIO_S1G_MISC_CFG_LANE_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = serdes_commit_mcb_s1g(regmap, serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct serdes_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) enum phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int submode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .idx = _idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .port = _port, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .mode = _mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .submode = _submode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .mux = _mux, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SERDES_MUX_SGMII(i, p, m, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SERDES_MUX_QSGMII(i, p, m, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct serdes_mux ocelot_serdes_muxes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SERDES_MUX_SGMII(SERDES1G(0), 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SERDES_MUX_SGMII(SERDES1G(1), 1, HSIO_HW_CFG_DEV1G_5_MODE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SERDES_MUX_SGMII(SERDES1G(1), 5, HSIO_HW_CFG_QSGMII_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) HSIO_HW_CFG_DEV1G_5_MODE, HSIO_HW_CFG_DEV1G_5_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SERDES_MUX_SGMII(SERDES1G(2), 2, HSIO_HW_CFG_DEV1G_4_MODE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SERDES_MUX_SGMII(SERDES1G(2), 4, HSIO_HW_CFG_QSGMII_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) HSIO_HW_CFG_DEV1G_4_MODE, HSIO_HW_CFG_DEV1G_4_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SERDES_MUX_SGMII(SERDES1G(3), 3, HSIO_HW_CFG_DEV1G_6_MODE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SERDES_MUX_SGMII(SERDES1G(3), 6, HSIO_HW_CFG_QSGMII_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) HSIO_HW_CFG_DEV1G_6_MODE, HSIO_HW_CFG_DEV1G_6_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SERDES_MUX_SGMII(SERDES1G(4), 4, HSIO_HW_CFG_QSGMII_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) HSIO_HW_CFG_DEV1G_4_MODE | HSIO_HW_CFG_DEV1G_9_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SERDES_MUX_SGMII(SERDES1G(4), 9, HSIO_HW_CFG_DEV1G_4_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) HSIO_HW_CFG_DEV1G_9_MODE, HSIO_HW_CFG_DEV1G_4_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) HSIO_HW_CFG_DEV1G_9_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SERDES_MUX_SGMII(SERDES1G(5), 5, HSIO_HW_CFG_QSGMII_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SERDES_MUX_SGMII(SERDES1G(5), 10, HSIO_HW_CFG_PCIE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) HSIO_HW_CFG_DEV1G_5_MODE | HSIO_HW_CFG_DEV2G5_10_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SERDES_MUX_QSGMII(SERDES6G(0), 4, HSIO_HW_CFG_QSGMII_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) HSIO_HW_CFG_QSGMII_ENA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SERDES_MUX_QSGMII(SERDES6G(0), 5, HSIO_HW_CFG_QSGMII_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) HSIO_HW_CFG_QSGMII_ENA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SERDES_MUX_QSGMII(SERDES6G(0), 6, HSIO_HW_CFG_QSGMII_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) HSIO_HW_CFG_QSGMII_ENA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SERDES_MUX_SGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SERDES_MUX_QSGMII(SERDES6G(0), 7, HSIO_HW_CFG_QSGMII_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) HSIO_HW_CFG_QSGMII_ENA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SERDES_MUX_SGMII(SERDES6G(1), 8, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SERDES_MUX_SGMII(SERDES6G(2), 10, HSIO_HW_CFG_PCIE_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) HSIO_HW_CFG_DEV2G5_10_MODE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) SERDES_MUX(SERDES6G(2), 10, PHY_MODE_PCIE, 0, HSIO_HW_CFG_PCIE_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) HSIO_HW_CFG_PCIE_ENA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int serdes_set_mode(struct phy *phy, enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct serdes_macro *macro = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* As of now only PHY_MODE_ETHERNET is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (mode != PHY_MODE_ETHERNET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) for (i = 0; i < ARRAY_SIZE(ocelot_serdes_muxes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (macro->idx != ocelot_serdes_muxes[i].idx ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mode != ocelot_serdes_muxes[i].mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) submode != ocelot_serdes_muxes[i].submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (submode != PHY_INTERFACE_MODE_QSGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) macro->port != ocelot_serdes_muxes[i].port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = regmap_update_bits(macro->ctrl->regs, HSIO_HW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ocelot_serdes_muxes[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ocelot_serdes_muxes[i].mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (macro->idx <= SERDES1G_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return serdes_init_s1g(macro->ctrl->regs, macro->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else if (macro->idx <= SERDES6G_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return serdes_init_s6g(macro->ctrl->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) macro->idx - (SERDES1G_MAX + 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ocelot_serdes_muxes[i].submode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* PCIe not supported yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct phy_ops serdes_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .set_mode = serdes_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct phy *serdes_simple_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct serdes_ctrl *ctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int port, idx, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (args->args_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) port = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) idx = args->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < SERDES_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct serdes_macro *macro = phy_get_drvdata(ctrl->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (idx != macro->idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* SERDES6G(0) is the only SerDes capable of QSGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (idx != SERDES6G(0) && macro->port >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) macro->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ctrl->phys[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int serdes_phy_create(struct serdes_ctrl *ctrl, u8 idx, struct phy **phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct serdes_macro *macro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *phy = devm_phy_create(ctrl->dev, NULL, &serdes_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (IS_ERR(*phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return PTR_ERR(*phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) macro = devm_kzalloc(ctrl->dev, sizeof(*macro), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!macro)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) macro->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) macro->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) macro->port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) phy_set_drvdata(*phy, macro);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int serdes_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct serdes_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ctrl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ctrl->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(ctrl->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return PTR_ERR(ctrl->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) for (i = 0; i < SERDES_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = serdes_phy_create(ctrl, i, &ctrl->phys[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_set_drvdata(&pdev->dev, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) provider = devm_of_phy_provider_register(ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) serdes_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct of_device_id serdes_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { .compatible = "mscc,vsc7514-serdes", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DEVICE_TABLE(of, serdes_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static struct platform_driver mscc_ocelot_serdes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .probe = serdes_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = "mscc,ocelot-serdes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .of_match_table = of_match_ptr(serdes_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) module_platform_driver(mscc_ocelot_serdes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_AUTHOR("Quentin Schulz <quentin.schulz@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MODULE_DESCRIPTION("SerDes driver for Microsemi Ocelot");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MODULE_LICENSE("Dual MIT/GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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