^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MediaTek USB3.1 gen2 xsphy Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* u2 phy banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SSUSB_SIFSLV_MISC 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SSUSB_SIFSLV_U2FREQ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SSUSB_SIFSLV_U2PHY_COM 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* u3 phy shared banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SSPXTP_SIFSLV_DIG_GLB 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SSPXTP_SIFSLV_PHYA_GLB 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* u3 phy banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SSPXTP_SIFSLV_DIG_LN_TOP 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SSPXTP_SIFSLV_DIG_LN_TX0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSPXTP_SIFSLV_DIG_LN_RX0 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSPXTP_SIFSLV_DIG_LN_DAIF 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SSPXTP_SIFSLV_PHYA_LN 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define P2F_RG_FREQDET_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define P2F_RG_CYCLECNT GENMASK(23, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XSP_U2FREQ_FMMONR1 ((SSUSB_SIFSLV_U2FREQ) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define P2F_RG_FRCK_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define P2F_USB_FM_VALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XSP_USBPHYACR0 ((SSUSB_SIFSLV_U2PHY_COM) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define P2A0_RG_INTR_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define P2A1_RG_INTR_CAL GENMASK(23, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define P2A1_RG_VRT_SEL GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define P2A1_RG_TERM_SEL GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define P2A5_RG_HSTX_SRCAL_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define P2A6_RG_BC11_SW_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define P2D_FORCE_IDDIG BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define P2D_RG_VBUSVALID BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define P2D_RG_SESSEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define P2D_RG_AVALID BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define P2D_RG_IDDIG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XSP_REF_CLK 26 /* MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XSP_SLEW_RATE_COEF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XSP_SR_COEF_DIVISOR 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XSP_FM_DET_CYCLE_CNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct xsphy_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct clk *ref_clk; /* reference clock of anolog phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* only for HQA test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int efuse_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int efuse_tx_imp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int efuse_rx_imp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* u2 eye diagram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int eye_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int eye_vrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int eye_term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mtk_xsphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *glb_base; /* only shared u3 sif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct xsphy_instance **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int nphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int src_coef; /* coefficient for slew rate calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void __iomem *pbase = inst->port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int calib_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int fm_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* use force value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (inst->eye_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* enable USB ring oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) tmp = readl(pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) tmp |= P2A5_RG_HSTX_SRCAL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(tmp, pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) udelay(1); /* wait clock stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* enable free run clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tmp |= P2F_RG_FRCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* set cycle count as 1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) tmp = readl(pbase + XSP_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tmp &= ~(P2F_RG_CYCLECNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tmp |= P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(tmp, pbase + XSP_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* enable frequency meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tmp = readl(pbase + XSP_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tmp |= P2F_RG_FREQDET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(tmp, pbase + XSP_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* ignore return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (tmp & P2F_USB_FM_VALID), 10, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* disable frequency meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp = readl(pbase + XSP_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp &= ~P2F_RG_FREQDET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(tmp, pbase + XSP_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* disable free run clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tmp &= ~P2F_RG_FRCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (fm_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* (1024 / FM_OUT) x reference clock frequency x coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tmp = xsphy->src_ref_clk * xsphy->src_coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* if FM detection fail, set default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) calib_val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) inst->index, fm_out, calib_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xsphy->src_ref_clk, xsphy->src_coef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* set HS slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tmp = readl(pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tmp &= ~P2A5_RG_HSTX_SRCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tmp |= P2A5_RG_HSTX_SRCTRL_VAL(calib_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(tmp, pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* disable USB ring oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tmp = readl(pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tmp &= ~P2A5_RG_HSTX_SRCAL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(tmp, pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *pbase = inst->port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* DP/DM BC1.1 path Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tmp = readl(pbase + XSP_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) tmp &= ~P2A6_RG_BC11_SW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel(tmp, pbase + XSP_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmp = readl(pbase + XSP_USBPHYACR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmp |= P2A0_RG_INTR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(tmp, pbase + XSP_USBPHYACR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __iomem *pbase = inst->port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 index = inst->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tmp = readl(pbase + XSP_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tmp |= P2A6_RG_OTG_VBUSCMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(tmp, pbase + XSP_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp = readl(pbase + XSP_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp |= P2D_RG_VBUSVALID | P2D_RG_AVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp &= ~P2D_RG_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(tmp, pbase + XSP_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void __iomem *pbase = inst->port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 index = inst->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tmp = readl(pbase + XSP_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tmp &= ~P2A6_RG_OTG_VBUSCMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writel(tmp, pbase + XSP_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tmp = readl(pbase + XSP_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) tmp &= ~(P2D_RG_VBUSVALID | P2D_RG_AVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tmp |= P2D_RG_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(tmp, pbase + XSP_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct xsphy_instance *inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum phy_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tmp = readl(inst->port_base + XSP_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case PHY_MODE_USB_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) case PHY_MODE_USB_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tmp |= P2D_FORCE_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tmp &= ~P2D_RG_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case PHY_MODE_USB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(tmp, inst->port_base + XSP_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void phy_parse_property(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct device *dev = &inst->phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) switch (inst->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case PHY_TYPE_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) device_property_read_u32(dev, "mediatek,efuse-intr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) &inst->efuse_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) device_property_read_u32(dev, "mediatek,eye-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) &inst->eye_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) device_property_read_u32(dev, "mediatek,eye-vrt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) &inst->eye_vrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) device_property_read_u32(dev, "mediatek,eye-term",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &inst->eye_term);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) inst->efuse_intr, inst->eye_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) inst->eye_vrt, inst->eye_term);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) device_property_read_u32(dev, "mediatek,efuse-intr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) &inst->efuse_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) device_property_read_u32(dev, "mediatek,efuse-tx-imp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) &inst->efuse_tx_imp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) device_property_read_u32(dev, "mediatek,efuse-rx-imp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) &inst->efuse_rx_imp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) inst->efuse_intr, inst->efuse_tx_imp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) inst->efuse_rx_imp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(xsphy->dev, "incompatible phy type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void u2_phy_props_set(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void __iomem *pbase = inst->port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (inst->efuse_intr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tmp = readl(pbase + XSP_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tmp &= ~P2A1_RG_INTR_CAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tmp |= P2A1_RG_INTR_CAL_VAL(inst->efuse_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(tmp, pbase + XSP_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (inst->eye_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tmp = readl(pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tmp &= ~P2A5_RG_HSTX_SRCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) tmp |= P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel(tmp, pbase + XSP_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (inst->eye_vrt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tmp = readl(pbase + XSP_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tmp &= ~P2A1_RG_VRT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tmp |= P2A1_RG_VRT_SEL_VAL(inst->eye_vrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) writel(tmp, pbase + XSP_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (inst->eye_term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tmp = readl(pbase + XSP_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tmp &= ~P2A1_RG_TERM_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tmp |= P2A1_RG_TERM_SEL_VAL(inst->eye_term);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(tmp, pbase + XSP_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void u3_phy_props_set(struct mtk_xsphy *xsphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct xsphy_instance *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) void __iomem *pbase = inst->port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (inst->efuse_intr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) tmp = readl(xsphy->glb_base + SSPXTP_PHYA_GLB_00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp &= ~RG_XTP_GLB_BIAS_INTR_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tmp |= RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writel(tmp, xsphy->glb_base + SSPXTP_PHYA_GLB_00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (inst->efuse_tx_imp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tmp = readl(pbase + SSPXTP_PHYA_LN_04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) tmp &= ~RG_XTP_LN0_TX_IMPSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) tmp |= RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel(tmp, pbase + SSPXTP_PHYA_LN_04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (inst->efuse_rx_imp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tmp = readl(pbase + SSPXTP_PHYA_LN_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tmp &= ~RG_XTP_LN0_RX_IMPSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) tmp |= RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) writel(tmp, pbase + SSPXTP_PHYA_LN_14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int mtk_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct xsphy_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = clk_prepare_enable(inst->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(xsphy->dev, "failed to enable ref_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) switch (inst->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case PHY_TYPE_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u2_phy_instance_init(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u2_phy_props_set(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u3_phy_props_set(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(xsphy->dev, "incompatible phy type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) clk_disable_unprepare(inst->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int mtk_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct xsphy_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (inst->type == PHY_TYPE_USB2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u2_phy_instance_power_on(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u2_phy_slew_rate_calibrate(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int mtk_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct xsphy_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (inst->type == PHY_TYPE_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u2_phy_instance_power_off(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int mtk_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct xsphy_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) clk_disable_unprepare(inst->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct xsphy_instance *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (inst->type == PHY_TYPE_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u2_phy_instance_set_mode(xsphy, inst, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct phy *mtk_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct mtk_xsphy *xsphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct xsphy_instance *inst = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct device_node *phy_np = args->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (args->args_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(dev, "invalid number of cells in 'phy' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (index = 0; index < xsphy->nphys; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (phy_np == xsphy->phys[index]->phy->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) inst = xsphy->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!inst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(dev, "failed to find appropriate phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) inst->type = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!(inst->type == PHY_TYPE_USB2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) inst->type == PHY_TYPE_USB3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(dev, "unsupported phy type: %d\n", inst->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) phy_parse_property(xsphy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return inst->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct phy_ops mtk_xsphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .init = mtk_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .exit = mtk_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .power_on = mtk_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .power_off = mtk_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .set_mode = mtk_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct of_device_id mtk_xsphy_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { .compatible = "mediatek,xsphy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int mtk_xsphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct device_node *child_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct resource *glb_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct mtk_xsphy *xsphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int port, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) xsphy = devm_kzalloc(dev, sizeof(*xsphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!xsphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) xsphy->nphys = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) xsphy->phys = devm_kcalloc(dev, xsphy->nphys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sizeof(*xsphy->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!xsphy->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) xsphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) platform_set_drvdata(pdev, xsphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) glb_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* optional, may not exist if no u3 phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (glb_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* get banks shared by multiple u3 phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR(xsphy->glb_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(dev, "failed to remap glb regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return PTR_ERR(xsphy->glb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) xsphy->src_ref_clk = XSP_REF_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) xsphy->src_coef = XSP_SLEW_RATE_COEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* update parameters of slew rate calibrate if exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &xsphy->src_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) for_each_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct xsphy_instance *inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!inst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) xsphy->phys[port] = inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) phy = devm_phy_create(dev, child_np, &mtk_xsphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_err(dev, "failed to create phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) retval = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) retval = of_address_to_resource(child_np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(dev, "failed to get address resource(id-%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) inst->port_base = devm_ioremap_resource(&phy->dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (IS_ERR(inst->port_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_err(dev, "failed to remap phy regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) retval = PTR_ERR(inst->port_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) inst->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) inst->index = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) phy_set_drvdata(phy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) port++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) inst->ref_clk = devm_clk_get(&phy->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (IS_ERR(inst->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) retval = PTR_ERR(inst->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct platform_driver mtk_xsphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .probe = mtk_xsphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "mtk-xsphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .of_match_table = mtk_xsphy_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) module_platform_driver(mtk_xsphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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