^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Stanley Chu <stanley.chu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* mphy register and offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MP_GLB_DIG_8C 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FRC_PLL_ISO_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PLL_ISO_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FRC_FRC_PWR_ON BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PLL_PWR_ON BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MP_LN_DIG_RX_9C 0xA09C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FSM_DIFZ_FRC BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MP_LN_DIG_RX_AC 0xA0AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FRC_RX_SQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RX_SQ_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MP_LN_RX_44 0xB044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FRC_CDR_PWR_ON BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CDR_PWR_ON BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FRC_CDR_ISO_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CDR_ISO_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct ufs_mtk_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct clk *mp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk *unipro_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return readl(phy->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) writel(val, phy->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val = mphy_readl(phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mphy_writel(phy, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = mphy_readl(phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) val &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mphy_writel(phy, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev = phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) phy->unipro_clk = devm_clk_get(dev, "unipro");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (IS_ERR(phy->unipro_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_err(dev, "failed to get clock: unipro");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return PTR_ERR(phy->unipro_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) phy->mp_clk = devm_clk_get(dev, "mp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (IS_ERR(phy->mp_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(dev, "failed to get clock: mp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return PTR_ERR(phy->mp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* release DA_MP_PLL_PWR_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* release DA_MP_PLL_ISO_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* release DA_MP_CDR_PWR_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* release DA_MP_CDR_ISO_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* release DA_MP_RX0_SQ_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* delay 1us to wait DIFZ stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* release DIFZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* force DIFZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* force DA_MP_RX0_SQ_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* force DA_MP_CDR_ISO_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* force DA_MP_CDR_PWR_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* force DA_MP_PLL_ISO_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* force DA_MP_PLL_PWR_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int ufs_mtk_phy_power_on(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = clk_prepare_enable(phy->unipro_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(phy->dev, "unipro_clk enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = clk_prepare_enable(phy->mp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(phy->dev, "mp_clk enable failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto out_unprepare_unipro_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ufs_mtk_phy_set_active(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) out_unprepare_unipro_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk_disable_unprepare(phy->unipro_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int ufs_mtk_phy_power_off(struct phy *generic_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ufs_mtk_phy_set_deep_hibern(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk_disable_unprepare(phy->unipro_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk_disable_unprepare(phy->mp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct phy_ops ufs_mtk_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .power_on = ufs_mtk_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .power_off = ufs_mtk_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int ufs_mtk_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ufs_mtk_phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) phy->mmio = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(phy->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return PTR_ERR(phy->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = ufs_mtk_phy_clk_init(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) generic_phy = devm_phy_create(dev, NULL, &ufs_mtk_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(generic_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) phy_set_drvdata(generic_phy, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct of_device_id ufs_mtk_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {.compatible = "mediatek,mt8183-ufsphy"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_DEVICE_TABLE(of, ufs_mtk_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct platform_driver ufs_mtk_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .probe = ufs_mtk_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .of_match_table = ufs_mtk_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "ufs_mtk_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) module_platform_driver(ufs_mtk_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MODULE_DESCRIPTION("Universal Flash Storage (UFS) MediaTek MPHY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_AUTHOR("Stanley Chu <stanley.chu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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