^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* version V1 sub-banks offset base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* banks shared by multiple phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* u2 phy bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* u3/pcie/sata phy banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SSUSB_SIFSLV_V1_U3PHYD 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SSUSB_SIFSLV_V1_U3PHYA 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* version V2 sub-banks offset base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* u2 phy banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SSUSB_SIFSLV_V2_MISC 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SSUSB_SIFSLV_V2_U2FREQ 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* u3/pcie/sata phy banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SSUSB_SIFSLV_V2_SPLLC 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SSUSB_SIFSLV_V2_CHIP 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SSUSB_SIFSLV_V2_U3PHYD 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SSUSB_SIFSLV_V2_U3PHYA 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define U3P_USBPHYACR0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PA0_RG_U2PLL_FORCE_ON BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PA0_RG_USB20_INTR_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define U3P_USBPHYACR1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PA1_RG_INTR_CAL GENMASK(23, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PA1_RG_VRT_SEL GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PA1_RG_TERM_SEL GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define U3P_USBPHYACR2 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define U3P_USBPHYACR5 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define U3P_USBPHYACR6 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PA6_RG_U2_BC11_SW_EN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PA6_RG_U2_DISCTH GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PA6_RG_U2_SQTH GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define U3P_U2PHYACR4 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define P2C_RG_USB20_GPIO_CTL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define P2C_USB20_GPIO_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define U3D_U2PHYDCR0 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define U3P_U2PHYDTM0 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define P2C_FORCE_UART_EN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define P2C_FORCE_DATAIN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define P2C_FORCE_DM_PULLDOWN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define P2C_FORCE_DP_PULLDOWN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define P2C_FORCE_XCVRSEL BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define P2C_FORCE_SUSPENDM BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define P2C_FORCE_TERMSEL BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define P2C_RG_DATAIN GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define P2C_RG_DMPULLDOWN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define P2C_RG_DPPULLDOWN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define P2C_RG_XCVRSEL GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define P2C_RG_SUSPENDM BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define P2C_RG_TERMSEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define P2C_DTM0_PART_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define U3P_U2PHYDTM1 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define P2C_RG_UART_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define P2C_FORCE_IDDIG BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define P2C_RG_VBUSVALID BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define P2C_RG_SESSEND BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define P2C_RG_AVALID BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define P2C_RG_IDDIG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define U3P_U2PHYBC12C 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define P2C_RG_CHGDT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define U3P_U3_CHIP_GPIO_CTLD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define P3C_REG_IP_SW_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define P3C_FORCE_IP_SW_RST BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define U3P_U3_CHIP_GPIO_CTLE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define P3C_RG_SWRST_U3_PHYD BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define U3P_U3_PHYA_REG0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define U3P_U3_PHYA_REG1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define U3P_U3_PHYA_REG6 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define U3P_U3_PHYA_REG9 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define U3P_U3_PHYA_DA_REG0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define U3P_U3_PHYA_DA_REG4 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define U3P_U3_PHYA_DA_REG5 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define U3P_U3_PHYA_DA_REG6 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define U3P_U3_PHYA_DA_REG7 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define U3P_U3_PHYA_DA_REG20 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define U3P_U3_PHYA_DA_REG25 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define U3P_U3_PHYD_LFPS1 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define P3D_RG_FWAKE_TH GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define U3P_U3_PHYD_CDR1 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define U3P_U3_PHYD_RXDET1 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define U3P_U3_PHYD_RXDET2 0x12c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define U3P_SPLLC_XTALCTL3 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define U3P_U2FREQ_FMCR0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define P2F_RG_MONCLK_SEL GENMASK(27, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define P2F_RG_FREQDET_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define P2F_RG_CYCLECNT GENMASK(23, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define U3P_U2FREQ_VALUE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define U3P_U2FREQ_FMMONR1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define P2F_USB_FM_VALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define P2F_RG_FRCK_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define U3P_REF_CLK 26 /* MHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define U3P_SLEW_RATE_COEF 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define U3P_SR_COEF_DIVISOR 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define U3P_FM_DET_CYCLE_CNT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* SATA register setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PHYD_CTRL_SIGNAL_MODE4 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* CDR Charge Pump P-path current adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PHYD_DESIGN_OPTION2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Symbol lock count selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PHYD_DESIGN_OPTION9 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* COMWAK GAP width window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RG_TG_MAX_MSK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* COMINIT GAP width window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RG_T2_MAX_MSK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* COMWAK GAP width window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RG_TG_MIN_MSK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* COMINIT GAP width window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define RG_T2_MIN_MSK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define RG_T2_MIN_VAL(x) (0x1f & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ANA_RG_CTRL_SIGNAL1 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ANA_RG_CTRL_SIGNAL4 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Loop filter R1 resistance adjustment for Gen1 speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ANA_RG_CTRL_SIGNAL6 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* I-path capacitance adjustment for Gen1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* RX Gen1 LEQ tuning step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) enum mtk_phy_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MTK_PHY_V1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MTK_PHY_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct mtk_phy_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* avoid RX sensitivity level degradation only for mt8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bool avoid_rx_sen_degradation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) enum mtk_phy_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct u2phy_banks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) void __iomem *fmreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void __iomem *com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct u3phy_banks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __iomem *spllc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void __iomem *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void __iomem *phyd; /* include u3phyd_bank2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __iomem *phya; /* include u3phya_da */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct mtk_phy_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) void __iomem *port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct u2phy_banks u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct u3phy_banks u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct clk *ref_clk; /* reference clock of (digital) phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct clk *da_ref_clk; /* reference clock of analog phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int eye_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int eye_vrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int eye_term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int discth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bool bc12_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct mtk_tphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void __iomem *sif_base; /* only shared sif */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const struct mtk_phy_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct mtk_phy_instance **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int nphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int src_coef; /* coefficient for slew rate calibrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) void __iomem *fmreg = u2_banks->fmreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) void __iomem *com = u2_banks->com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int calibration_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int fm_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* use force value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (instance->eye_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* enable USB ring oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tmp = readl(com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(tmp, com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /*enable free run clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tmp |= P2F_RG_FRCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* set cycle count as 1024, and select u2 channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (tphy->pdata->version == MTK_PHY_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* enable frequency meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tmp |= P2F_RG_FREQDET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* ignore return value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (tmp & P2F_USB_FM_VALID), 10, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) fm_out = readl(fmreg + U3P_U2FREQ_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* disable frequency meter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tmp &= ~P2F_RG_FREQDET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*disable free run clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tmp &= ~P2F_RG_FRCK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (fm_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* ( 1024 / FM_OUT ) x reference clock frequency x coef */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tmp = tphy->src_ref_clk * tphy->src_coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* if FM detection fail, set default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) calibration_val = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) instance->index, fm_out, calibration_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) tphy->src_ref_clk, tphy->src_coef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* set HS slew rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tmp = readl(com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writel(tmp, com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* disable USB ring oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tmp = readl(com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) writel(tmp, com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void u3_phy_instance_init(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct u3phy_banks *u3_banks = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* gating PCIe Analog XTAL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* gating XSQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp &= ~P3A_RG_RX_DAC_MUX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tmp &= ~P3A_RG_TX_EIDLE_CM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tmp &= ~P3D_RG_FWAKE_TH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tmp &= ~P3D_RG_RXDET_STB2_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void u2_phy_instance_init(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) void __iomem *com = u2_banks->com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 index = instance->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* switch to USB function, and enable usb pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tmp = readl(com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) tmp &= ~P2C_RG_UART_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) writel(tmp, com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tmp = readl(com + U3P_USBPHYACR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tmp |= PA0_RG_USB20_INTR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel(tmp, com + U3P_USBPHYACR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* disable switch 100uA current to SSUSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) tmp = readl(com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) writel(tmp, com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) tmp = readl(com + U3P_U2PHYACR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tmp &= ~P2C_U2_GPIO_CTR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) writel(tmp, com + U3P_U2PHYACR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (tphy->pdata->avoid_rx_sen_degradation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) tmp = readl(com + U3P_USBPHYACR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) writel(tmp, com + U3P_USBPHYACR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tmp = readl(com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) writel(tmp, com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) tmp = readl(com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) writel(tmp, com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) tmp = readl(com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) tmp &= ~PA6_RG_U2_SQTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) tmp |= PA6_RG_U2_SQTH_VAL(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel(tmp, com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) void __iomem *com = u2_banks->com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 index = instance->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* OTG Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tmp = readl(com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) writel(tmp, com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) tmp = readl(com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) tmp &= ~P2C_RG_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writel(tmp, com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (tphy->pdata->avoid_rx_sen_degradation && index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) tmp = readl(com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) writel(tmp, com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) void __iomem *com = u2_banks->com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 index = instance->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* OTG Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) tmp = readl(com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) writel(tmp, com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) tmp = readl(com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) tmp |= P2C_RG_SESSEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writel(tmp, com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (tphy->pdata->avoid_rx_sen_degradation && index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tmp = readl(com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) writel(tmp, com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void u2_phy_instance_exit(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) void __iomem *com = u2_banks->com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 index = instance->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (tphy->pdata->avoid_rx_sen_degradation && index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) tmp = readl(com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) writel(tmp, com + U3D_U2PHYDCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) tmp = readl(com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tmp &= ~P2C_FORCE_SUSPENDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) writel(tmp, com + U3P_U2PHYDTM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void u2_phy_instance_set_mode(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct mtk_phy_instance *instance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) enum phy_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case PHY_MODE_USB_DEVICE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case PHY_MODE_USB_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) tmp |= P2C_FORCE_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) tmp &= ~P2C_RG_IDDIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case PHY_MODE_USB_OTG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void pcie_phy_instance_init(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct u3phy_banks *u3_banks = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (tphy->pdata->version != MTK_PHY_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* ref clk drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tmp &= ~P3A_RG_CLKDRV_AMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tmp &= ~P3A_RG_CLKDRV_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* SSC delta -5000ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) tmp &= ~P3A_RG_PLL_DELTA_PE2H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* change pll BW 0.6M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tmp &= ~P3A_RG_PLL_IR_PE2H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) tmp &= ~P3A_RG_PLL_BP_PE2H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Tx Detect Rx Timing: 10us -> 5us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) tmp &= ~P3D_RG_RXDET_STB2_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* wait for PCIe subsys register to active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) usleep_range(2500, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct u3phy_banks *bank = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct u3phy_banks *bank = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static void sata_phy_instance_init(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct u3phy_banks *u3_banks = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) void __iomem *phyd = u3_banks->phyd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* charge current adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) tmp = readl(phyd + PHYD_DESIGN_OPTION2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) tmp &= ~RG_LOCK_CNT_SEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) writel(tmp, phyd + PHYD_DESIGN_OPTION2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) tmp = readl(phyd + PHYD_DESIGN_OPTION9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RG_T2_MAX_MSK | RG_TG_MAX_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writel(tmp, phyd + PHYD_DESIGN_OPTION9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) tmp &= ~RG_IDRV_0DB_GEN1_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void phy_v1_banks_init(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct u3phy_banks *u3_banks = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) switch (instance->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) case PHY_TYPE_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u2_banks->misc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_err(tphy->dev, "incompatible PHY type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void phy_v2_banks_init(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct u3phy_banks *u3_banks = &instance->u3_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) switch (instance->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case PHY_TYPE_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_err(tphy->dev, "incompatible PHY type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static void phy_parse_property(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct device *dev = &instance->phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (instance->type != PHY_TYPE_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) device_property_read_u32(dev, "mediatek,eye-src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) &instance->eye_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) device_property_read_u32(dev, "mediatek,eye-vrt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) &instance->eye_vrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) device_property_read_u32(dev, "mediatek,eye-term",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) &instance->eye_term);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) device_property_read_u32(dev, "mediatek,intr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &instance->intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) device_property_read_u32(dev, "mediatek,discth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) &instance->discth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) instance->bc12_en, instance->eye_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) instance->eye_vrt, instance->eye_term,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) instance->intr, instance->discth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static void u2_phy_props_set(struct mtk_tphy *tphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct mtk_phy_instance *instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct u2phy_banks *u2_banks = &instance->u2_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) void __iomem *com = u2_banks->com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (instance->bc12_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) tmp = readl(com + U3P_U2PHYBC12C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writel(tmp, com + U3P_U2PHYBC12C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (instance->eye_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) tmp = readl(com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) writel(tmp, com + U3P_USBPHYACR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (instance->eye_vrt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) tmp = readl(com + U3P_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) tmp &= ~PA1_RG_VRT_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) writel(tmp, com + U3P_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (instance->eye_term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) tmp = readl(com + U3P_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) tmp &= ~PA1_RG_TERM_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) writel(tmp, com + U3P_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (instance->intr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) tmp = readl(com + U3P_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) tmp &= ~PA1_RG_INTR_CAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) writel(tmp, com + U3P_USBPHYACR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (instance->discth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) tmp = readl(com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) tmp &= ~PA6_RG_U2_DISCTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) writel(tmp, com + U3P_USBPHYACR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int mtk_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct mtk_phy_instance *instance = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ret = clk_prepare_enable(instance->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_err(tphy->dev, "failed to enable ref_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = clk_prepare_enable(instance->da_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dev_err(tphy->dev, "failed to enable da_ref\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) clk_disable_unprepare(instance->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) switch (instance->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case PHY_TYPE_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u2_phy_instance_init(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u2_phy_props_set(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u3_phy_instance_init(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pcie_phy_instance_init(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) sata_phy_instance_init(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) dev_err(tphy->dev, "incompatible PHY type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) clk_disable_unprepare(instance->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) clk_disable_unprepare(instance->da_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int mtk_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct mtk_phy_instance *instance = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (instance->type == PHY_TYPE_USB2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u2_phy_instance_power_on(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) hs_slew_rate_calibrate(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else if (instance->type == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) pcie_phy_instance_power_on(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int mtk_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct mtk_phy_instance *instance = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (instance->type == PHY_TYPE_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u2_phy_instance_power_off(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) else if (instance->type == PHY_TYPE_PCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) pcie_phy_instance_power_off(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int mtk_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct mtk_phy_instance *instance = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (instance->type == PHY_TYPE_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u2_phy_instance_exit(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) clk_disable_unprepare(instance->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) clk_disable_unprepare(instance->da_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct mtk_phy_instance *instance = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (instance->type == PHY_TYPE_USB2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) u2_phy_instance_set_mode(tphy, instance, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static struct phy *mtk_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct mtk_tphy *tphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct mtk_phy_instance *instance = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct device_node *phy_np = args->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (args->args_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dev_err(dev, "invalid number of cells in 'phy' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) for (index = 0; index < tphy->nphys; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (phy_np == tphy->phys[index]->phy->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) instance = tphy->phys[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_err(dev, "failed to find appropriate phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) instance->type = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (!(instance->type == PHY_TYPE_USB2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) instance->type == PHY_TYPE_USB3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) instance->type == PHY_TYPE_PCIE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) instance->type == PHY_TYPE_SATA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_err(dev, "unsupported device type: %d\n", instance->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (tphy->pdata->version == MTK_PHY_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) phy_v1_banks_init(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) } else if (tphy->pdata->version == MTK_PHY_V2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) phy_v2_banks_init(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dev_err(dev, "phy version is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) phy_parse_property(tphy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return instance->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const struct phy_ops mtk_tphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .init = mtk_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .exit = mtk_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .power_on = mtk_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .power_off = mtk_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .set_mode = mtk_phy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const struct mtk_phy_pdata tphy_v1_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .avoid_rx_sen_degradation = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .version = MTK_PHY_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const struct mtk_phy_pdata tphy_v2_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .avoid_rx_sen_degradation = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .version = MTK_PHY_V2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const struct mtk_phy_pdata mt8173_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .avoid_rx_sen_degradation = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .version = MTK_PHY_V1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct of_device_id mtk_tphy_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int mtk_tphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct device_node *child_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct resource *sif_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct mtk_tphy *tphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int port, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!tphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) tphy->pdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (!tphy->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) tphy->nphys = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) tphy->phys = devm_kcalloc(dev, tphy->nphys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) sizeof(*tphy->phys), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (!tphy->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) tphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) platform_set_drvdata(pdev, tphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* SATA phy of V1 needn't it if not shared with PCIe or USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (sif_res && tphy->pdata->version == MTK_PHY_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* get banks shared by multiple phys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) tphy->sif_base = devm_ioremap_resource(dev, sif_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (IS_ERR(tphy->sif_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dev_err(dev, "failed to remap sif regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return PTR_ERR(tphy->sif_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) tphy->src_ref_clk = U3P_REF_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) tphy->src_coef = U3P_SLEW_RATE_COEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* update parameters of slew rate calibrate if exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) &tphy->src_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) for_each_child_of_node(np, child_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct mtk_phy_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!instance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) tphy->phys[port] = instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) phy = devm_phy_create(dev, child_np, &mtk_tphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_err(dev, "failed to create phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) retval = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) retval = of_address_to_resource(child_np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_err(dev, "failed to get address resource(id-%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) instance->port_base = devm_ioremap_resource(&phy->dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (IS_ERR(instance->port_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dev_err(dev, "failed to remap phy regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) retval = PTR_ERR(instance->port_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) instance->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) instance->index = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) phy_set_drvdata(phy, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) port++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) instance->ref_clk = devm_clk_get_optional(&phy->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (IS_ERR(instance->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) retval = PTR_ERR(instance->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) instance->da_ref_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) devm_clk_get_optional(&phy->dev, "da_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (IS_ERR(instance->da_ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) retval = PTR_ERR(instance->da_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static struct platform_driver mtk_tphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .probe = mtk_tphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .name = "mtk-tphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .of_match_table = mtk_tphy_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) module_platform_driver(mtk_tphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) MODULE_DESCRIPTION("MediaTek T-PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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