Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Chunhui Dai <chunhui.dai@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _MTK_HDMI_PHY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _MTK_HDMI_PHY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct mtk_hdmi_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct mtk_hdmi_phy_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	bool pll_default_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	const struct clk_ops *hdmi_phy_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mtk_hdmi_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct mtk_hdmi_phy_conf *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	struct clk *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct clk_hw pll_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	unsigned long pll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	unsigned char drv_imp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned char drv_imp_d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned char drv_imp_d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned char drv_imp_d0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	unsigned int ibias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	unsigned int ibias_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			     u32 bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			   u32 bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		       u32 val, u32 mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif /* _MTK_HDMI_PHY_H */