^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jie Qiu <jie.qiu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "phy-mtk-hdmi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) static int mtk_hdmi_phy_power_on(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static int mtk_hdmi_phy_power_off(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static const struct phy_ops mtk_hdmi_phy_dev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) .power_on = mtk_hdmi_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .power_off = mtk_hdmi_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *reg = hdmi_phy->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) tmp = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) tmp &= ~bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *reg = hdmi_phy->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) tmp = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) tmp |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 val, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *reg = hdmi_phy->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) tmp = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) tmp = (tmp & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) writel(tmp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return container_of(hw, struct mtk_hdmi_phy, pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int mtk_hdmi_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ret = clk_prepare_enable(hdmi_phy->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) hdmi_phy->conf->hdmi_phy_enable_tmds(hdmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int mtk_hdmi_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clk_disable_unprepare(hdmi_phy->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct phy_ops *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (hdmi_phy && hdmi_phy->conf &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) hdmi_phy->conf->hdmi_phy_enable_tmds &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hdmi_phy->conf->hdmi_phy_disable_tmds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return &mtk_hdmi_phy_dev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_err(hdmi_phy->dev, "Failed to get dev ops of phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void mtk_hdmi_phy_clk_get_data(struct mtk_hdmi_phy *hdmi_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct clk_init_data *clk_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clk_init->flags = hdmi_phy->conf->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int mtk_hdmi_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mtk_hdmi_phy *hdmi_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char *ref_clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_init_data clk_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .parent_names = (const char * const *)&ref_clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) hdmi_phy = devm_kzalloc(dev, sizeof(*hdmi_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) hdmi_phy->regs = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (IS_ERR(hdmi_phy->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = PTR_ERR(hdmi_phy->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(dev, "Failed to get memory resource: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ref_clk = devm_clk_get(dev, "pll_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (IS_ERR(ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = PTR_ERR(ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(&pdev->dev, "Failed to get PLL reference clock: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ref_clk_name = __clk_get_name(ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = of_property_read_string(dev->of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &clk_init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_err(dev, "Failed to read clock-output-names: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hdmi_phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) hdmi_phy->conf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (struct mtk_hdmi_phy_conf *)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mtk_hdmi_phy_clk_get_data(hdmi_phy, &clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hdmi_phy->pll_hw.init = &clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(hdmi_phy->pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = PTR_ERR(hdmi_phy->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(dev, "Failed to register PLL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = of_property_read_u32(dev->of_node, "mediatek,ibias",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) &hdmi_phy->ibias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(&pdev->dev, "Failed to get ibias: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = of_property_read_u32(dev->of_node, "mediatek,ibias_up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &hdmi_phy->ibias_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(&pdev->dev, "Failed to get ibias up: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_info(dev, "Using default TX DRV impedance: 4.2k/36\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) hdmi_phy->drv_imp_clk = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hdmi_phy->drv_imp_d2 = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) hdmi_phy->drv_imp_d1 = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hdmi_phy->drv_imp_d0 = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) phy = devm_phy_create(dev, NULL, mtk_hdmi_phy_dev_get_ops(hdmi_phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(dev, "Failed to create HDMI PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) phy_set_drvdata(phy, hdmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dev_err(dev, "Failed to register HDMI PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (hdmi_phy->conf->pll_default_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) hdmi_phy->pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id mtk_hdmi_phy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "mediatek,mt2701-hdmi-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .data = &mtk_hdmi_phy_2701_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .compatible = "mediatek,mt8173-hdmi-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .data = &mtk_hdmi_phy_8173_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct platform_driver mtk_hdmi_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .probe = mtk_hdmi_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "mediatek-hdmi-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .of_match_table = mtk_hdmi_phy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) module_platform_driver(mtk_hdmi_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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