^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jie Qiu <jie.qiu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "phy-mtk-hdmi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HDMI_CON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RG_HDMITX_PLL_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PLL_FBKDIV_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PLL_FBKSEL_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RG_HDMITX_PLL_PREDIV (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PREDIV_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RG_HDMITX_PLL_POSDIV (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define POSDIV_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RG_HDMITX_PLL_IR (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_IR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RG_HDMITX_PLL_IC (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_IC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RG_HDMITX_PLL_BP (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_BP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RG_HDMITX_PLL_BR (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_BR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RG_HDMITX_PLL_BC (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_BC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HDMI_CON1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RG_HDMITX_PLL_DIVEN (0x7 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLL_DIVEN_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RG_HDMITX_PLL_AUTOK_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RG_HDMITX_PLL_BAND (0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RG_HDMITX_PLL_REF_SEL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RG_HDMITX_PLL_BIAS_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RG_HDMITX_PLL_TXDIV_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RG_HDMITX_PLL_TXDIV (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLL_TXDIV_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RG_HDMITX_PLL_LVROD_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RG_HDMITX_PLL_MONVC_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RG_HDMITX_PLL_MONCK_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RG_HDMITX_PLL_MONREF_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RG_HDMITX_PLL_TST_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RG_HDMITX_PLL_TST_CK_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RG_HDMITX_PLL_TST_SEL (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HDMI_CON2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RG_HDMITX_EN_TX_CKLDO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HDMI_CON3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RG_HDMITX_SER_EN (0xf << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RG_HDMITX_PRD_EN (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RG_HDMITX_PRD_IMP_EN (0xf << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RG_HDMITX_DRV_EN (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RG_HDMITX_DRV_IMP_EN (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DRV_IMP_EN_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RG_HDMITX_MHLCK_FORCE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RG_HDMITX_MHLCK_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RG_HDMITX_SER_DIN_SEL (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RG_HDMITX_SER_BIST_TOG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RG_HDMITX_SER_DIN_TOG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RG_HDMITX_SER_CLKDIG_INV BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HDMI_CON4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PRD_IBIAS_CLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PRD_IBIAS_D2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PRD_IBIAS_D1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PRD_IBIAS_D0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HDMI_CON5 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DRV_IBIAS_CLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DRV_IBIAS_D2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DRV_IBIAS_D1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DRV_IBIAS_D0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HDMI_CON6 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DRV_IMP_CLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DRV_IMP_D2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DRV_IMP_D1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DRV_IMP_D0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HDMI_CON7 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RG_HDMITX_SER_DIN (0x3ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RG_HDMITX_CHLDC_TST (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RG_HDMITX_CHLCK_TST (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RG_HDMITX_RESERVE (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HDMI_CON8 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RGS_HDMITX_2T1_LEV (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RGS_HDMITX_2T1_EDG (0xf << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RGS_HDMITX_5T1_LEV (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RGS_HDMITX_5T1_EDG (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RGS_HDMITX_PLUG_TST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hdmi_phy->pll_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (rate <= 74250000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *parent_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *parent_rate = rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int pre_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int pre_ibias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int hdmi_ibias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int imp_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (rate <= 27000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pre_div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else if (rate <= 74250000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pre_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pre_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (0x1 << PLL_BR_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) RG_HDMITX_PLL_BR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (rate < 165000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) RG_HDMITX_PRD_IMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pre_ibias = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) imp_en = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) hdmi_ibias = hdmi_phy->ibias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) RG_HDMITX_PRD_IMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pre_ibias = 0x6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) imp_en = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hdmi_ibias = hdmi_phy->ibias_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (pre_ibias << PRD_IBIAS_D2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (pre_ibias << PRD_IBIAS_D1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (pre_ibias << PRD_IBIAS_D0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) RG_HDMITX_PRD_IBIAS_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) RG_HDMITX_PRD_IBIAS_D2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) RG_HDMITX_PRD_IBIAS_D1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) RG_HDMITX_PRD_IBIAS_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (imp_en << DRV_IMP_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) RG_HDMITX_DRV_IMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) RG_HDMITX_DRV_IBIAS_CLK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) RG_HDMITX_DRV_IBIAS_D2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) RG_HDMITX_DRV_IBIAS_D1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) RG_HDMITX_DRV_IBIAS_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return hdmi_phy->pll_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const struct clk_ops mtk_hdmi_phy_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .prepare = mtk_hdmi_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .unprepare = mtk_hdmi_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .set_rate = mtk_hdmi_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .round_rate = mtk_hdmi_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .recalc_rate = mtk_hdmi_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) RG_HDMITX_DRV_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) usleep_range(100, 150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) RG_HDMITX_SER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DESCRIPTION("MediaTek MT8173 HDMI PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags