^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Chunhui Dai <chunhui.dai@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "phy-mtk-hdmi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HDMI_CON0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RG_HDMITX_DRV_IBIAS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RG_HDMITX_EN_SER 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RG_HDMITX_EN_SER_MASK (0x0f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RG_HDMITX_EN_SLDO 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RG_HDMITX_EN_SLDO_MASK (0x0f << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RG_HDMITX_EN_PRED 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RG_HDMITX_EN_PRED_MASK (0x0f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RG_HDMITX_EN_IMP 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RG_HDMITX_EN_IMP_MASK (0x0f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RG_HDMITX_EN_DRV 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RG_HDMITX_EN_DRV_MASK (0x0f << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HDMI_CON1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RG_HDMITX_PRED_IBIAS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RG_HDMITX_PRED_IMP (0x01 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RG_HDMITX_DRV_IMP 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RG_HDMITX_DRV_IMP_MASK (0x3f << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HDMI_CON2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RG_HDMITX_EN_TX_CKLDO (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RG_HDMITX_EN_TX_POSDIV (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RG_HDMITX_TX_POSDIV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RG_HDMITX_EN_MBIAS (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HDMI_CON4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RG_HDMITX_RESERVE_MASK (0xffffffff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HDMI_CON6 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RG_HTPLL_BR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RG_HTPLL_BR_MASK (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RG_HTPLL_BC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RG_HTPLL_BC_MASK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RG_HTPLL_BP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RG_HTPLL_BP_MASK (0x0f << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RG_HTPLL_IR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RG_HTPLL_IR_MASK (0x0f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RG_HTPLL_IC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RG_HTPLL_IC_MASK (0x0f << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RG_HTPLL_POSDIV 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RG_HTPLL_POSDIV_MASK (0x03 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RG_HTPLL_PREDIV 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RG_HTPLL_PREDIV_MASK (0x03 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RG_HTPLL_FBKSEL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RG_HTPLL_FBKSEL_MASK (0x03 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RG_HTPLL_RLH_EN (0x01 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RG_HTPLL_FBKDIV 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RG_HTPLL_FBKDIV_MASK (0x7f << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RG_HTPLL_EN (0x01 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HDMI_CON7 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RG_HTPLL_AUTOK_EN (0x01 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RG_HTPLL_DIVEN 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RG_HTPLL_DIVEN_MASK (0x07 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 pos_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rate <= 64000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pos_div = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else if (rate <= 128000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pos_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pos_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) RG_HTPLL_IC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) RG_HTPLL_IR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) RG_HDMITX_TX_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) RG_HTPLL_FBKSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) RG_HTPLL_FBKDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) RG_HTPLL_DIVEN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RG_HTPLL_BP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RG_HTPLL_BC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) RG_HTPLL_BR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) RG_HDMITX_PRED_IBIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RG_HDMITX_DRV_IMP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) RG_HDMITX_DRV_IBIAS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long out_rate, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val = (readl(hdmi_phy->regs + HDMI_CON6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) out_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) out_rate = parent_rate / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) out_rate = parent_rate / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val = (readl(hdmi_phy->regs + HDMI_CON6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) out_rate *= (val + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val = (readl(hdmi_phy->regs + HDMI_CON2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) & RG_HDMITX_TX_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) out_rate /= 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return out_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct clk_ops mtk_hdmi_phy_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .prepare = mtk_hdmi_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .unprepare = mtk_hdmi_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .set_rate = mtk_hdmi_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .round_rate = mtk_hdmi_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .recalc_rate = mtk_hdmi_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) usleep_range(80, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .flags = CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .pll_default_off = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MODULE_AUTHOR("Chunhui Dai <chunhui.dai@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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