^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Linaro, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Rob Herring <robh@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on vendor driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 Marvell Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* USB PXA1928 PHY mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_28NM_PLL_REG0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PHY_28NM_PLL_REG1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_28NM_CAL_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHY_28NM_TX_REG0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_28NM_TX_REG1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_28NM_RX_REG0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHY_28NM_RX_REG1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHY_28NM_DIG_REG0 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_28NM_DIG_REG1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_28NM_TEST_REG0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_28NM_TEST_REG1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PHY_28NM_MOC_REG 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_28NM_PHY_RESERVE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PHY_28NM_OTG_REG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_28NM_CHRG_DET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PHY_28NM_CTRL_REG0 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PHY_28NM_CTRL_REG1 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_28NM_CTRL_REG2 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_28NM_CTRL_REG3 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PHY_28NM_PLL_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_28NM_PLL_READY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_28NM_PLL_SELLPFR_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_28NM_PLL_SELLPFR_MASK (0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_28NM_PLL_FBDIV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_28NM_PLL_FBDIV_MASK (0x1ff << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PHY_28NM_PLL_ICP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PHY_28NM_PLL_ICP_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PHY_28NM_PLL_REFDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_28NM_PLL_REFDIV_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* PHY_28NM_PLL_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PHY_28NM_PLL_PU_BY_REG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PHY_28NM_PLL_PU_PLL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* PHY_28NM_CAL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_28NM_PLL_PLLCAL_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_28NM_PLL_IMPCAL_DONE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_28NM_PLL_KVCO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_28NM_PLL_KVCO_MASK (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_28NM_PLL_CAL12_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PHY_28NM_PLL_CAL12_MASK (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PHY_28NM_IMPCAL_VTH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_28NM_IMPCAL_VTH_MASK (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_28NM_PLLCAL_START_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PHY_28NM_IMPCAL_START_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PHY_28NM_TX_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_28NM_TX_PU_BY_REG BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PHY_28NM_TX_PU_ANA BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PHY_28NM_TX_AMP_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PHY_28NM_TX_AMP_MASK (0x7 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* PHY_28NM_RX_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PHY_28NM_RX_SQ_THRESH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PHY_28NM_RX_SQ_THRESH_MASK (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* PHY_28NM_RX_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PHY_28NM_RX_SQCAL_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* PHY_28NM_DIG_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PHY_28NM_DIG_BITSTAFFING_ERR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PHY_28NM_DIG_SYNC_ERR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PHY_28NM_DIG_SQ_FILT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PHY_28NM_DIG_SQ_FILT_MASK (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PHY_28NM_DIG_SQ_BLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PHY_28NM_DIG_SQ_BLK_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PHY_28NM_DIG_SYNC_NUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PHY_28NM_DIG_SYNC_NUM_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PHY_28NM_PLL_LOCK_BYPASS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* PHY_28NM_OTG_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PHY_28NM_OTG_CONTROL_BY_PIN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PHY_28NM_OTG_PU_OTG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PHY_28NM_CHGDTC_PD_EN_SHIFT_28 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PHY_28NM_CTRL3_OVERWRITE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PHY_28NM_CTRL3_VBUS_VALID BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PHY_28NM_CTRL3_AVALID BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PHY_28NM_CTRL3_BVALID BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mv_usb2_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return readl_poll_timeout(reg, val, ((val & mask) == mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 1000, 1000 * ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int mv_usb2_phy_28nm_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct platform_device *pdev = mv_phy->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clk_prepare_enable(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* PHY_28NM_PLL_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) reg = readl(base + PHY_28NM_PLL_REG0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ~(PHY_28NM_PLL_SELLPFR_MASK | PHY_28NM_PLL_FBDIV_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) | PHY_28NM_PLL_ICP_MASK | PHY_28NM_PLL_REFDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) | 0xf0 << PHY_28NM_PLL_FBDIV_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) | 0x3 << PHY_28NM_PLL_ICP_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | 0xd << PHY_28NM_PLL_REFDIV_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) base + PHY_28NM_PLL_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* PHY_28NM_PLL_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg = readl(base + PHY_28NM_PLL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) base + PHY_28NM_PLL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* PHY_28NM_TX_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PHY_28NM_TX_PU_ANA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) base + PHY_28NM_TX_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* PHY_28NM_RX_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) base + PHY_28NM_RX_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* PHY_28NM_DIG_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg = readl(base + PHY_28NM_DIG_REG0) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ~(PHY_28NM_DIG_BITSTAFFING_ERR | PHY_28NM_DIG_SYNC_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PHY_28NM_DIG_SQ_FILT_MASK | PHY_28NM_DIG_SQ_BLK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PHY_28NM_DIG_SYNC_NUM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PHY_28NM_PLL_LOCK_BYPASS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) base + PHY_28NM_DIG_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* PHY_28NM_OTG_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Calibration Timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * ____________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * CAL START ___|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * ____________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * CAL_DONE ___________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * | 400us |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Make sure PHY Calibration is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = wait_for_reg(base + PHY_28NM_CAL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = wait_for_reg(base + PHY_28NM_RX_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PHY_28NM_RX_SQCAL_DONE, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Make sure PHY PLL is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_disable_unprepare(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int mv_usb2_phy_28nm_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(readl(base + PHY_28NM_CTRL_REG3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) base + PHY_28NM_CTRL_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int mv_usb2_phy_28nm_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(readl(base + PHY_28NM_CTRL_REG3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ~(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) | PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) base + PHY_28NM_CTRL_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int mv_usb2_phy_28nm_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) val = readw(base + PHY_28NM_PLL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val &= ~PHY_28NM_PLL_PU_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writew(val, base + PHY_28NM_PLL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* power down PHY Analog part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val = readw(base + PHY_28NM_TX_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val &= ~PHY_28NM_TX_PU_ANA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writew(val, base + PHY_28NM_TX_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* power down PHY OTG part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val = readw(base + PHY_28NM_OTG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val &= ~PHY_28NM_OTG_PU_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writew(val, base + PHY_28NM_OTG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_disable_unprepare(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct phy_ops usb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .init = mv_usb2_phy_28nm_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .power_on = mv_usb2_phy_28nm_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .power_off = mv_usb2_phy_28nm_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .exit = mv_usb2_phy_28nm_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int mv_usb2_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct mv_usb2_phy *mv_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!mv_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mv_phy->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (IS_ERR(mv_phy->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(&pdev->dev, "failed to get clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return PTR_ERR(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mv_phy->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (IS_ERR(mv_phy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return PTR_ERR(mv_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &usb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (IS_ERR(mv_phy->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return PTR_ERR(mv_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) phy_set_drvdata(mv_phy->phy, mv_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct of_device_id mv_usbphy_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .compatible = "marvell,pxa1928-usb-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct platform_driver mv_usb2_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .probe = mv_usb2_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "mv-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .of_match_table = of_match_ptr(mv_usbphy_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_platform_driver(mv_usb2_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("Marvell USB2 phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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