^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Linaro, Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Rob Herring <robh@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on vendor driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 Marvell Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Chao Xie <xiechao.mail@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_28NM_HSIC_CTRL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHY_28NM_HSIC_IMPCAL_CAL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_28NM_HSIC_PLL_CTRL01 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PHY_28NM_HSIC_PLL_CTRL2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_28NM_HSIC_INT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_28NM_HSIC_PLL_FBDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHY_28NM_HSIC_PLL_REFDIV_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_28NM_HSIC_S2H_PU_PLL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_28NM_HSIC_H2S_PLL_LOCK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_28NM_HSIC_S2H_HSIC_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S2H_DRV_SE0_4RESUME BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHY_28NM_HSIC_H2S_IMPCAL_DONE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_28NM_HSIC_CONNECT_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PHY_28NM_HSIC_HS_READY_INT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct mv_hsic_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return readl_poll_timeout(reg, val, ((val & mask) == mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 1000, 1000 * ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int mv_hsic_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct platform_device *pdev = mv_phy->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk_prepare_enable(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Set reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(0x1 << PHY_28NM_HSIC_PLL_SELLPFR_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0xf0 << PHY_28NM_HSIC_PLL_FBDIV_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0xd << PHY_28NM_HSIC_PLL_REFDIV_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) base + PHY_28NM_HSIC_PLL_CTRL01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Turn on PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PHY_28NM_HSIC_S2H_PU_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) base + PHY_28NM_HSIC_PLL_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Make sure PHY PLL is locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PHY_28NM_HSIC_H2S_PLL_LOCK, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_disable_unprepare(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int mv_hsic_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct platform_device *pdev = mv_phy->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = readl(base + PHY_28NM_HSIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Avoid SE0 state when resume for some device will take it as reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg &= ~S2H_DRV_SE0_4RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg |= PHY_28NM_HSIC_S2H_HSIC_EN; /* Enable HSIC PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writel(reg, base + PHY_28NM_HSIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Calibration Timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * ____________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * CAL START ___|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * ____________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * CAL_DONE ___________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * | 400us |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Make sure PHY Calibration is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Waiting for HSIC connect int*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = wait_for_reg(base + PHY_28NM_HSIC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PHY_28NM_HSIC_CONNECT_INT, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int mv_hsic_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) base + PHY_28NM_HSIC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int mv_hsic_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __iomem *base = mv_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Turn off PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ~PHY_28NM_HSIC_S2H_PU_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) base + PHY_28NM_HSIC_PLL_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk_disable_unprepare(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct phy_ops hsic_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .init = mv_hsic_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .power_on = mv_hsic_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .power_off = mv_hsic_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .exit = mv_hsic_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int mv_hsic_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct mv_hsic_phy *mv_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!mv_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mv_phy->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (IS_ERR(mv_phy->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(&pdev->dev, "failed to get clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return PTR_ERR(mv_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mv_phy->base = devm_ioremap_resource(&pdev->dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (IS_ERR(mv_phy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return PTR_ERR(mv_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &hsic_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (IS_ERR(mv_phy->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return PTR_ERR(mv_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) phy_set_drvdata(mv_phy->phy, mv_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct of_device_id mv_hsic_phy_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .compatible = "marvell,pxa1928-hsic-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_DEVICE_TABLE(of, mv_hsic_phy_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct platform_driver mv_hsic_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .probe = mv_hsic_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = "mv-hsic-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .of_match_table = of_match_ptr(mv_hsic_phy_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) module_platform_driver(mv_hsic_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_DESCRIPTION("Marvell HSIC phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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