^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Igal Liberman <igall@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Miquèl Raynal <miquel.raynal@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Marvell A3700 UTMI PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Armada 3700 UTMI PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB2_PHY_PLL_CTRL_REG0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_REF_DIV_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_REF_DIV_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_REF_DIV_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_FB_DIV_OFF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_FB_DIV_MASK GENMASK(24, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_FB_DIV_96 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_SEL_LPFR_OFF 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_SEL_LPFR_MASK GENMASK(29, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_READY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USB2_PHY_CAL_CTRL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHY_PLLCAL_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHY_IMPCAL_DONE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USB2_RX_CHAN_CTRL1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USB2PHY_SQCAL_DONE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USB2_PHY_OTG_CTRL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_PU_OTG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USB2_PHY_CHRGR_DETECT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PHY_CDP_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_DCP_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_PD_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHY_PU_CHRG_DTC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHY_CDP_DM_AUTO BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_ENSWITCH_DP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_ENSWITCH_DM BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Armada 3700 USB miscellaneous registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB2_PHY_CTRL(usb32) (usb32 ? 0x20 : 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RB_USB2PHY_PU BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USB2_DP_PULLDN_DEV_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB2_DM_PULLDN_DEV_MODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RB_USB2PHY_SUSPM(usb32) (usb32 ? BIT(14) : BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PLL_LOCK_DELAY_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PLL_LOCK_TIMEOUT_US 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * struct mvebu_a3700_utmi_caps - PHY capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @usb32: Flag indicating which PHY is in use (impacts the register map):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * - The UTMI PHY wired to the USB3/USB2 controller (otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - The UTMI PHY wired to the USB2 controller (host only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @ops: PHY operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mvebu_a3700_utmi_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int usb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct phy_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * struct mvebu_a3700_utmi - PHY driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @regs: PHY registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @usb_misc: Regmap with USB miscellaneous registers including PHY ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @caps: PHY capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @phy: PHY handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct mvebu_a3700_utmi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regmap *usb_misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct mvebu_a3700_utmi_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int mvebu_a3700_utmi_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev = &phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int usb32 = utmi->caps->usb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Setup PLL. 40MHz clock used to be the default, being 25MHz now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * See "PLL Settings for Typical REFCLK" table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = readl(utmi->regs + USB2_PHY_PLL_CTRL_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg &= ~(PLL_REF_DIV_MASK | PLL_FB_DIV_MASK | PLL_SEL_LPFR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg |= (PLL_REF_DIV_5 << PLL_REF_DIV_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (PLL_FB_DIV_96 << PLL_FB_DIV_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel(reg, utmi->regs + USB2_PHY_PLL_CTRL_REG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Enable PHY pull up and disable USB2 suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (usb32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Power up OTG module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = readl(utmi->regs + USB2_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg |= PHY_PU_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Disable PHY charger detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg = readl(utmi->regs + USB2_PHY_CHRGR_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg &= ~(PHY_CDP_EN | PHY_DCP_EN | PHY_PD_EN | PHY_PU_CHRG_DTC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PHY_CDP_DM_AUTO | PHY_ENSWITCH_DP | PHY_ENSWITCH_DM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(reg, utmi->regs + USB2_PHY_CHRGR_DETECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Disable PHY DP/DM pull-down (used for device mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_update_bits(utmi->usb_misc, USB2_PHY_CTRL(usb32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) USB2_DP_PULLDN_DEV_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) USB2_DM_PULLDN_DEV_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Wait for PLL calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg & PHY_PLLCAL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_err(dev, "Failed to end USB2 PLL calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Wait for impedance calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = readl_poll_timeout(utmi->regs + USB2_PHY_CAL_CTRL, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg & PHY_IMPCAL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(dev, "Failed to end USB2 impedance calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Wait for squelch calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = readl_poll_timeout(utmi->regs + USB2_RX_CHAN_CTRL1, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg & USB2PHY_SQCAL_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(dev, "Failed to end USB2 unknown calibration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Wait for PLL to be locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = readl_poll_timeout(utmi->regs + USB2_PHY_PLL_CTRL_REG0, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg & PLL_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(dev, "Failed to lock USB2 PLL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int mvebu_a3700_utmi_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mvebu_a3700_utmi *utmi = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int usb32 = utmi->caps->usb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Disable PHY pull-up and enable USB2 suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg = readl(utmi->regs + USB2_PHY_CTRL(usb32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reg &= ~(RB_USB2PHY_PU | RB_USB2PHY_SUSPM(usb32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(reg, utmi->regs + USB2_PHY_CTRL(usb32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Power down OTG module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (usb32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) reg = readl(utmi->regs + USB2_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) reg &= ~PHY_PU_OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(reg, utmi->regs + USB2_PHY_OTG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct phy_ops mvebu_a3700_utmi_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .power_on = mvebu_a3700_utmi_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .power_off = mvebu_a3700_utmi_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct mvebu_a3700_utmi_caps mvebu_a3700_utmi_otg_phy_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .usb32 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .ops = &mvebu_a3700_utmi_phy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct mvebu_a3700_utmi_caps mvebu_a3700_utmi_host_phy_caps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .usb32 = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ops = &mvebu_a3700_utmi_phy_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct of_device_id mvebu_a3700_utmi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .compatible = "marvell,a3700-utmi-otg-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .data = &mvebu_a3700_utmi_otg_phy_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .compatible = "marvell,a3700-utmi-host-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .data = &mvebu_a3700_utmi_host_phy_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_DEVICE_TABLE(of, mvebu_a3700_utmi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int mvebu_a3700_utmi_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct mvebu_a3700_utmi *utmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!utmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Get UTMI memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) utmi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(utmi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return PTR_ERR(utmi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Get miscellaneous Host/PHY region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) utmi->usb_misc = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "marvell,usb-misc-reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (IS_ERR(utmi->usb_misc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "Missing USB misc purpose system controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PTR_ERR(utmi->usb_misc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Retrieve PHY capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) utmi->caps = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Instantiate the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) utmi->phy = devm_phy_create(dev, NULL, utmi->caps->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(utmi->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(dev, "Failed to create the UTMI PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return PTR_ERR(utmi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) phy_set_drvdata(utmi->phy, utmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Ensure the PHY is powered off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) utmi->caps->ops->power_off(utmi->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct platform_driver mvebu_a3700_utmi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .probe = mvebu_a3700_utmi_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "mvebu-a3700-utmi-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .of_match_table = mvebu_a3700_utmi_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) module_platform_driver(mvebu_a3700_utmi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MODULE_AUTHOR("Igal Liberman <igall@marvell.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DESCRIPTION("Marvell EBU A3700 UTMI PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags