Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2018 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *   Evan Wang <xswang@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   Miquèl Raynal <miquel.raynal@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * SMC call initial support done by Grzegorz Jaszczyk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MVEBU_A3700_COMPHY_LANES		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MVEBU_A3700_COMPHY_PORTS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* COMPHY Fast SMC function identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define COMPHY_SIP_POWER_ON			0x82000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define COMPHY_SIP_POWER_OFF			0x82000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define COMPHY_SIP_PLL_LOCK			0x82000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define COMPHY_FW_MODE_SATA			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define COMPHY_FW_MODE_SGMII			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define COMPHY_FW_MODE_HS_SGMII			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define COMPHY_FW_MODE_USB3H			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define COMPHY_FW_MODE_USB3D			0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define COMPHY_FW_MODE_PCIE			0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define COMPHY_FW_MODE_RXAUI			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define COMPHY_FW_MODE_XFI			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define COMPHY_FW_MODE_SFI			0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define COMPHY_FW_MODE_USB3			0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define COMPHY_FW_SPEED_1_25G			0 /* SGMII 1G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define COMPHY_FW_SPEED_2_5G			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define COMPHY_FW_SPEED_3_125G			2 /* SGMII 2.5G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define COMPHY_FW_SPEED_5G			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define COMPHY_FW_SPEED_5_15625G		4 /* XFI 5G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define COMPHY_FW_SPEED_6G			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define COMPHY_FW_SPEED_10_3125G		6 /* XFI 10G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define COMPHY_FW_SPEED_MAX			0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define COMPHY_FW_MODE(mode)			((mode) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define COMPHY_FW_NET(mode, idx, speed)		(COMPHY_FW_MODE(mode) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 						 ((idx) << 8) |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 						 ((speed) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define COMPHY_FW_PCIE(mode, idx, speed, width)	(COMPHY_FW_NET(mode, idx, speed) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 						 ((width) << 18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct mvebu_a3700_comphy_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	enum phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int submode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.lane = _lane,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.mode = _mode,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.submode = _smode,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.port = _port,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.fw_mode = _fw,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				    COMPHY_FW_MODE_USB3H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				    COMPHY_FW_MODE_SGMII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				    COMPHY_FW_MODE_HS_SGMII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* lane 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				    COMPHY_FW_MODE_PCIE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				    COMPHY_FW_MODE_SGMII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				    COMPHY_FW_MODE_HS_SGMII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* lane 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				    COMPHY_FW_MODE_SATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				    COMPHY_FW_MODE_USB3H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mvebu_a3700_comphy_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	enum phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int submode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				  unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ret = res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	switch (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case SMCCC_RET_SUCCESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case SMCCC_RET_NOT_SUPPORTED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 					  enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					  int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* Unused PHY mux value is 0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (mode == PHY_MODE_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	for (i = 0; i < n; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		if (mvebu_a3700_comphy_modes[i].lane == lane &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		    mvebu_a3700_comphy_modes[i].port == port &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		    mvebu_a3700_comphy_modes[i].mode == mode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		    mvebu_a3700_comphy_modes[i].submode == submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (i == n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return mvebu_a3700_comphy_modes[i].fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				       int submode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	int fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (submode == PHY_INTERFACE_MODE_1000BASEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		submode = PHY_INTERFACE_MODE_SGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 						 submode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (fw_mode < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dev_err(lane->dev, "invalid COMPHY mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Just remember the mode, ->power_on() will do the real setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	lane->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	lane->submode = submode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int mvebu_a3700_comphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u32 fw_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 						 lane->mode, lane->submode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (fw_mode < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dev_err(lane->dev, "invalid COMPHY mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return fw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	switch (lane->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	case PHY_MODE_USB_HOST_SS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		fw_param = COMPHY_FW_MODE(fw_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case PHY_MODE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		fw_param = COMPHY_FW_MODE(fw_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case PHY_MODE_ETHERNET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		switch (lane->submode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				lane->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			fw_param = COMPHY_FW_NET(fw_mode, lane->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 						 COMPHY_FW_SPEED_1_25G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				lane->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			fw_param = COMPHY_FW_NET(fw_mode, lane->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 						 COMPHY_FW_SPEED_3_125G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			dev_err(lane->dev, "unsupported PHY submode (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				lane->submode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case PHY_MODE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		fw_param = COMPHY_FW_PCIE(fw_mode, lane->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					  COMPHY_FW_SPEED_5G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					  phy->attrs.bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (ret == -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		dev_err(lane->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			"unsupported SMC call, try updating your firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int mvebu_a3700_comphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct phy_ops mvebu_a3700_comphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.power_on	= mvebu_a3700_comphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.power_off	= mvebu_a3700_comphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.set_mode	= mvebu_a3700_comphy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 					    struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct mvebu_a3700_comphy_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	phy = of_phy_simple_xlate(dev, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	lane->port = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	for_each_available_child_of_node(pdev->dev.of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		struct mvebu_a3700_comphy_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		u32 lane_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = of_property_read_u32(child, "reg", &lane_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			dev_err(&pdev->dev, "invalid 'reg' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		if (!lane) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		phy = devm_phy_create(&pdev->dev, child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				      &mvebu_a3700_comphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		lane->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		lane->mode = PHY_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		lane->submode = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		lane->id = lane_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		lane->port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		phy_set_drvdata(phy, lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	provider = devm_of_phy_provider_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 						 mvebu_a3700_comphy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{ .compatible = "marvell,comphy-a3700" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct platform_driver mvebu_a3700_comphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.probe	= mvebu_a3700_comphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.name = "mvebu-a3700-comphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.of_match_table = mvebu_a3700_comphy_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) module_platform_driver(mvebu_a3700_comphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_DESCRIPTION("Common PHY driver for A3700");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_LICENSE("GPL v2");