^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018,2019 Lubomir Rintel <lkundrak@v3.sk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/soc/mmp/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define USB2_PLL_REG0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define USB2_PLL_REG1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USB2_TX_REG0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define USB2_TX_REG1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USB2_TX_REG2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define USB2_RX_REG0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USB2_RX_REG1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB2_RX_REG2 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB2_ANA_REG0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USB2_ANA_REG1 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USB2_ANA_REG2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USB2_DIG_REG0 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USB2_DIG_REG1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USB2_DIG_REG2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USB2_DIG_REG3 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USB2_TEST_REG0 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USB2_TEST_REG1 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USB2_TEST_REG2 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USB2_CHARGER_REG0 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USB2_OTG_REG0 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USB2_PHY_MON0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USB2_RESETVE_REG0 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USB2_ICID_REG0 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USB2_ICID_REG1 0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* USB2_PLL_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* This is for Ax stepping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USB2_PLL_FBDIV_SHIFT_MMP3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USB2_PLL_REFDIV_SHIFT_MMP3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USB2_PLL_VDD12_SHIFT_MMP3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB2_PLL_VDD18_SHIFT_MMP3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* This is for B0 stepping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB2_PLL_VDD18_SHIFT_MMP3_B0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB2_PLL_CAL12_SHIFT_MMP3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define USB2_PLL_KVCO_SHIFT_MMP3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define USB2_PLL_ICP_SHIFT_MMP3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USB2_PLL_ICP_MASK_MMP3 (0x7<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USB2_PLL_PU_PLL_SHIFT_MMP3 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USB2_PLL_PU_PLL_MASK (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USB2_PLL_READY_MASK_MMP3 (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* USB2_TX_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define USB2_TX_RCAL_START_SHIFT_MMP3 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* USB2_TX_REG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define USB2_TX_AMP_SHIFT_MMP3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define USB2_TX_AMP_MASK_MMP3 (0x7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define USB2_TX_VDD12_SHIFT_MMP3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* USB2_TX_REG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define USB2_TX_DRV_SLEWRATE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* USB2_RX_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define USB2_RX_SQ_THRESH_SHIFT_MMP3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* USB2_ANA_REG1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define USB2_ANA_PU_ANA_SHIFT_MMP3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* USB2_OTG_REG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define USB2_OTG_PU_OTG_SHIFT_MMP3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mmp3_usb_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static unsigned int u2o_get(void __iomem *base, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void u2o_set(void __iomem *base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reg |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel_relaxed(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void u2o_clear(void __iomem *base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg = readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg &= ~value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel_relaxed(reg, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) readl_relaxed(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int mmp3_usb_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __iomem *base = mmp3_usb_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (cpu_is_mmp3_a0()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) | USB2_PLL_REFDIV_MASK_MMP3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u2o_set(base, USB2_PLL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 0xd << USB2_PLL_REFDIV_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) | 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else if (cpu_is_mmp3_b0()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) | USB2_PLL_FBDIV_MASK_MMP3_B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u2o_set(base, USB2_PLL_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0xd << USB2_PLL_REFDIV_SHIFT_MMP3_B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) | 0xf0 << USB2_PLL_FBDIV_SHIFT_MMP3_B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dev_err(&phy->dev, "unsupported silicon revision\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) | USB2_PLL_ICP_MASK_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) | USB2_PLL_KVCO_MASK_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) | USB2_PLL_CALI12_MASK_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | 1 << USB2_PLL_LOCK_BYPASS_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) | 3 << USB2_PLL_ICP_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | 3 << USB2_PLL_KVCO_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | 3 << USB2_PLL_CAL12_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) | USB2_TX_AMP_MASK_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) | USB2_TX_CK60_PHSEL_MASK_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) | 4 << USB2_TX_AMP_SHIFT_MMP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) | 4 << USB2_TX_CK60_PHSEL_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int mmp3_usb_phy_calibrate(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mmp3_usb_phy *mmp3_usb_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void __iomem *base = mmp3_usb_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * PLL VCO and TX Impedance Calibration Timing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * _____________________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * PU __________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * _____________________________
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * VCOCAL START _________|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * ___
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * REG_RCAL_START ________________| |________|_______
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * | 200us | 400us | 40| 400us | USB PHY READY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) udelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) udelay(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) udelay(400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) loops = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) loops++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (loops > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(&phy->dev, "PLL_READY not set after 100mS.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct phy_ops mmp3_usb_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .init = mmp3_usb_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .calibrate = mmp3_usb_phy_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct of_device_id mmp3_usb_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .compatible = "marvell,mmp3-usb-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_DEVICE_TABLE(of, mmp3_usb_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int mmp3_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct resource *resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct mmp3_usb_phy *mmp3_usb_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mmp3_usb_phy = devm_kzalloc(dev, sizeof(*mmp3_usb_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!mmp3_usb_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mmp3_usb_phy->base = devm_ioremap_resource(dev, resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (IS_ERR(mmp3_usb_phy->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(dev, "failed to remap PHY regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return PTR_ERR(mmp3_usb_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mmp3_usb_phy->phy = devm_phy_create(dev, NULL, &mmp3_usb_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(mmp3_usb_phy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return PTR_ERR(mmp3_usb_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) phy_set_drvdata(mmp3_usb_phy->phy, mmp3_usb_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (IS_ERR(provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(dev, "failed to register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct platform_driver mmp3_usb_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .probe = mmp3_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "mmp3-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .of_match_table = mmp3_usb_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) module_platform_driver(mmp3_usb_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_DESCRIPTION("Marvell MMP3 USB PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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