^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Marvell Technology Group Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Antoine Tenart <antoine.tenart@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jisheng Zhang <jszhang@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define USB_PHY_PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define USB_PHY_PLL_CONTROL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define USB_PHY_TX_CTRL0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define USB_PHY_TX_CTRL1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USB_PHY_TX_CTRL2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB_PHY_RX_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB_PHY_ANALOG 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* USB_PHY_PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_REF_DIV(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FEEDBACK_CLK_DIV(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* USB_PHY_PLL_CONTROL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_STABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_CTRL_PIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_CTRL_REG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLL_ON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PHASE_OFF_TOL_125 (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PHASE_OFF_TOL_250 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KVC0_CALIB (0x0 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define KVC0_REG_CTRL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define KVC0_HIGH (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define KVC0_LOW (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_BLK_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* USB_PHY_TX_CTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXT_HS_RCAL_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXT_FS_RCAL_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMPCAL_VTH_DIV(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXT_RS_RCAL_DIV(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXT_FS_RCAL_DIV(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* USB_PHY_TX_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TX_VDD15_14 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TX_VDD15_15 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TX_VDD15_16 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TX_VDD15_17 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TX_VDD12_VDD (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TX_VDD12_11 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TX_VDD12_12 (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TX_VDD12_13 (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LOW_VDD_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TX_OUT_AMP(x) ((x) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* USB_PHY_TX_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TX_CHAN_CTRL_REG(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DRV_SLEWRATE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMP_CAL_FS_HS_DLY_0 (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMP_CAL_FS_HS_DLY_1 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMP_CAL_FS_HS_DLY_3 (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FS_DRV_EN_MASK(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HS_DRV_EN_MASK(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* USB_PHY_RX_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PHASE_FREEZE_DLY_2_CL (0x0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHASE_FREEZE_DLY_4_CL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ACK_LENGTH_8_CL (0x0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ACK_LENGTH_12_CL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ACK_LENGTH_16_CL (0x2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ACK_LENGTH_20_CL (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SQ_LENGTH_3 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SQ_LENGTH_6 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SQ_LENGTH_9 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SQ_LENGTH_12 (0x3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DISCON_THRESHOLD_260 (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DISCON_THRESHOLD_270 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DISCON_THRESHOLD_280 (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DISCON_THRESHOLD_290 (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SQ_THRESHOLD(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LPF_COEF(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INTPL_CUR_10 (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define INTPL_CUR_20 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define INTPL_CUR_30 (0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define INTPL_CUR_40 (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* USB_PHY_ANALOG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ANA_PWR_UP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ANA_PWR_DOWN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define V2I_VCO_RATIO(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R_ROTATE_90 (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R_ROTATE_0 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MODE_TEST_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ANA_TEST_DC_CTRL(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const u32 phy_berlin_pll_dividers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Berlin 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Berlin 2CD/Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct phy_berlin_usb_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct reset_control *rst_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 pll_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int phy_berlin_usb_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reset_control_reset(priv->rst_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(priv->pll_divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) priv->base + USB_PHY_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) priv->base + USB_PHY_ANALOG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DISCON_THRESHOLD_270 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) priv->base + USB_PHY_TX_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) priv->base + USB_PHY_TX_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct phy_ops phy_berlin_usb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .power_on = phy_berlin_usb_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct of_device_id phy_berlin_usb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .compatible = "marvell,berlin2-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .data = &phy_berlin_pll_dividers[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .compatible = "marvell,berlin2cd-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .data = &phy_berlin_pll_dividers[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int phy_berlin_usb_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct of_device_id *match =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) of_match_device(phy_berlin_usb_of_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct phy_berlin_usb_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) priv->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(priv->rst_ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return PTR_ERR(priv->rst_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) priv->pll_divider = *((u32 *)match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(&pdev->dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) phy_provider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct platform_driver phy_berlin_usb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .probe = phy_berlin_usb_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = "phy-berlin-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .of_match_table = phy_berlin_usb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) module_platform_driver(phy_berlin_usb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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