^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell Berlin SATA PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Marvell Technology Group Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Antoine Ténart <antoine.tenart@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HOST_VSA_ADDR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HOST_VSA_DATA 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PORT_SCR_CTL 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PORT_VSR_ADDR 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PORT_VSR_DATA 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CONTROL_REGISTER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MBUS_SIZE_CONTROL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define POWER_DOWN_PHY0 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define POWER_DOWN_PHY1 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BG2_PHY_BASE 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BG2Q_PHY_BASE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* register 0x01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REF_FREF_SEL_25 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PHY_BERLIN_MODE_SATA (0x0 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* register 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USE_MAX_PLL_RATE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* register 0x23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DATA_BIT_WIDTH_10 (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DATA_BIT_WIDTH_20 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DATA_BIT_WIDTH_40 (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* register 0x25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_GEN_MAX_1_5 (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_GEN_MAX_3_0 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_GEN_MAX_6_0 (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct phy_berlin_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct phy_berlin_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct phy_berlin_desc **phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned nphys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 phy_base, u32 reg, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* set bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regval = readl(ctrl_reg + PORT_VSR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) regval &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) regval |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel(regval, ctrl_reg + PORT_VSR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int phy_berlin_sata_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct phy_berlin_desc *desc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Power on PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regval = readl(priv->base + HOST_VSA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) regval &= ~desc->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(regval, priv->base + HOST_VSA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Configure MBus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) regval = readl(priv->base + HOST_VSA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(regval, priv->base + HOST_VSA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* set PHY mode and ref freq to 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x00ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* set PHY up to 6 Gbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x0c00, PHY_GEN_MAX_6_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* set 40 bits width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x0c00, DATA_BIT_WIDTH_40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* use max pll rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x0000, USE_MAX_PLL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* set Gen3 controller speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) regval = readl(ctrl_reg + PORT_SCR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regval &= ~GENMASK(7, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regval |= 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(regval, ctrl_reg + PORT_SCR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int phy_berlin_sata_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct phy_berlin_desc *desc = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Power down PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regval = readl(priv->base + HOST_VSA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) regval |= desc->power_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(regval, priv->base + HOST_VSA_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct phy *phy_berlin_sata_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct phy_berlin_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (WARN_ON(args->args[0] >= priv->nphys))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (i = 0; i < priv->nphys; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (priv->phys[i]->index == args->args[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (i == priv->nphys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return priv->phys[i]->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct phy_ops phy_berlin_sata_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .power_on = phy_berlin_sata_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .power_off = phy_berlin_sata_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static u32 phy_berlin_power_down_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) POWER_DOWN_PHY0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) POWER_DOWN_PHY1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int phy_berlin_sata_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct phy_berlin_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->base = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!priv->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) priv->nphys = of_get_child_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (priv->nphys == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) priv->phys = devm_kcalloc(dev, priv->nphys, sizeof(*priv->phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!priv->phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) priv->phy_base = BG2_PHY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) priv->phy_base = BG2Q_PHY_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for_each_available_child_of_node(dev->of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct phy_berlin_desc *phy_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (of_property_read_u32(child, "reg", &phy_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(dev, "missing reg property in node %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(dev, "invalid reg in node %pOFn\n", child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!phy_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(dev, "failed to create PHY %d\n", phy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) phy_desc->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) phy_desc->power_bit = phy_berlin_power_down_bits[phy_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) phy_desc->index = phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) phy_set_drvdata(phy, phy_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) priv->phys[i++] = phy_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Make sure the PHY is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) phy_berlin_sata_power_off(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) phy_provider =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct of_device_id phy_berlin_sata_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .compatible = "marvell,berlin2-sata-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { .compatible = "marvell,berlin2q-sata-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct platform_driver phy_berlin_sata_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .probe = phy_berlin_sata_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .name = "phy-berlin-sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .of_match_table = phy_berlin_sata_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) module_platform_driver(phy_berlin_sata_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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