^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Partly derived from CP110 comphy driver by Antoine Tenart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * <antoine.tenart@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MAX_A38X_COMPHY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MAX_A38X_PORTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define COMPHY_CFG1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define COMPHY_CFG1_GEN_TX(x) ((x) << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define COMPHY_CFG1_GEN_TX_MSK COMPHY_CFG1_GEN_TX(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define COMPHY_CFG1_GEN_RX(x) ((x) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define COMPHY_CFG1_GEN_RX_MSK COMPHY_CFG1_GEN_RX(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GEN_SGMII_1_25GBPS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GEN_SGMII_3_125GBPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define COMPHY_STAT1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define COMPHY_STAT1_PLL_RDY_TX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define COMPHY_STAT1_PLL_RDY_RX BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define COMPHY_SELECTOR 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct a38x_comphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct a38x_comphy_lane {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct a38x_comphy *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct a38x_comphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { 4, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 0, 0, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0, 0, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct a38x_comphy *priv = lane->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (priv->conf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) conf = readl_relaxed(priv->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) conf |= BIT(lane->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) conf &= ~BIT(lane->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel(conf, priv->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int offset, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) val = readl_relaxed(lane->base + offset) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel(val | value, lane->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int gen_tx, unsigned int gen_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) a38x_comphy_set_reg(lane, COMPHY_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) COMPHY_CFG1_GEN_TX(gen_tx) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) COMPHY_CFG1_GEN_RX(gen_rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int offset, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (val & mask) == value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 1000, 150000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(lane->priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "comphy%u: timed out waiting for status\n", lane->n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * We only support changing the speed for comphys configured for GBE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Since that is all we do, we only poll for PLL ready status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (mode != PHY_MODE_ETHERNET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch (sub) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case PHY_INTERFACE_MODE_1000BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) gen = GEN_SGMII_1_25GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) gen = GEN_SGMII_3_125GBPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) a38x_set_conf(lane, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) a38x_comphy_set_speed(lane, gen, gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = a38x_comphy_poll(lane, COMPHY_STAT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) COMPHY_STAT1_PLL_RDY_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) COMPHY_STAT1_PLL_RDY_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) COMPHY_STAT1_PLL_RDY_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) COMPHY_STAT1_PLL_RDY_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) a38x_set_conf(lane, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct phy_ops a38x_comphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .set_mode = a38x_comphy_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct phy *a38x_comphy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct a38x_comphy_lane *lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (WARN_ON(args->args[0] >= MAX_A38X_PORTS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) phy = of_phy_simple_xlate(dev, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) lane = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (lane->port >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) lane->port = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val = (val >> (4 * lane->n)) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!gbe_mux[lane->n][lane->port] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val != gbe_mux[lane->n][lane->port]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_warn(lane->priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "comphy%u: not configured for GBE\n", lane->n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) phy = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int a38x_comphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct a38x_comphy *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "conf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) priv->conf = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(priv->conf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return PTR_ERR(priv->conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for_each_available_child_of_node(pdev->dev.of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = of_property_read_u32(child, "reg", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(&pdev->dev, "invalid 'reg' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) priv->lane[val].base = base + 0x28 * val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) priv->lane[val].priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) priv->lane[val].n = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) priv->lane[val].port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) phy_set_drvdata(phy, &priv->lane[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_set_drvdata(&pdev->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct of_device_id a38x_comphy_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .compatible = "marvell,armada-380-comphy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct platform_driver a38x_comphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .probe = a38x_comphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "armada-38x-comphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .of_match_table = a38x_comphy_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) module_platform_driver(a38x_comphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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