Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on the BSP (called "UGW") driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Copyright (C) 2016 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * TODO: PHY modes other than 36MHz (without "SSC")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCIE_PHY_PLL_CTRL1				0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PCIE_PHY_PLL_CTRL2				0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCIE_PHY_PLL_CTRL3				0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK	GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PCIE_PHY_PLL_CTRL4				0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCIE_PHY_PLL_CTRL5				0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PCIE_PHY_PLL_CTRL6				0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PCIE_PHY_PLL_CTRL7				0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCIE_PHY_PLL_A_CTRL1				0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCIE_PHY_PLL_A_CTRL2				0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN			BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PCIE_PHY_PLL_A_CTRL3				0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCIE_PHY_PLL_A_CTRL3_MMD_MASK			GENMASK(15, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCIE_PHY_PLL_STATUS				0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PCIE_PHY_TX1_CTRL1				0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCIE_PHY_TX1_CTRL1_FORCE_EN			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCIE_PHY_TX1_CTRL1_LOAD_EN			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PCIE_PHY_TX1_CTRL2				0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PCIE_PHY_TX1_CTRL3				0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PCIE_PHY_TX1_A_CTRL1				0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCIE_PHY_TX1_A_CTRL2				0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PCIE_PHY_TX1_MOD1				0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PCIE_PHY_TX1_MOD2				0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PCIE_PHY_TX1_MOD3				0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PCIE_PHY_TX2_CTRL1				0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PCIE_PHY_TX2_CTRL1_LOAD_EN			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PCIE_PHY_TX2_CTRL2				0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PCIE_PHY_TX2_A_CTRL1				0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PCIE_PHY_TX2_A_CTRL2				0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PCIE_PHY_TX2_MOD1				0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PCIE_PHY_TX2_MOD2				0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PCIE_PHY_TX2_MOD3				0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PCIE_PHY_RX1_CTRL1				0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PCIE_PHY_RX1_CTRL1_LOAD_EN			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PCIE_PHY_RX1_CTRL2				0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PCIE_PHY_RX1_CDR				0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PCIE_PHY_RX1_EI					0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PCIE_PHY_RX1_A_CTRL				0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct ltq_vrx200_pcie_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct phy			*phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	unsigned int			mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct device			*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct regmap			*phy_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct regmap			*rcu_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct clk			*pdi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct clk			*phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct reset_control		*phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct reset_control		*pcie_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32				rcu_ahb_endian_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32				rcu_ahb_endian_big_endian_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* PLL Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* increase the bias reference voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	/* Endcnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			   PCIE_PHY_TX1_CTRL1_FORCE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			   PCIE_PHY_TX1_CTRL1_FORCE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* predrv_ser_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* ctrl_lim */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* predrv_ser_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			   0x4700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* RTERM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Improved 100MHz clock output  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* Reduced CDR BW to avoid glitches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void pcie_phy_36mhz_mode_setup(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			   PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			   PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			   PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			   PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			   PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			   PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			   FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			   PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* const_sdm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			   PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			   FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				      0xee));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* pllmod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				       tmp, ((tmp & 0x0070) == 0x0070), 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				       10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	static const struct reg_default slices[] =  {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			.reg = PCIE_PHY_TX1_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			.def = PCIE_PHY_TX1_CTRL1_LOAD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			.reg = PCIE_PHY_TX2_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			.def = PCIE_PHY_TX2_CTRL1_LOAD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			.reg = PCIE_PHY_RX1_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			.def = PCIE_PHY_RX1_CTRL1_LOAD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	for (i = 0; i < ARRAY_SIZE(slices); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		/* enable load_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		regmap_update_bits(priv->phy_regmap, slices[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				   slices[i].def, slices[i].def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		/* disable load_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		regmap_update_bits(priv->phy_regmap, slices[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				   slices[i].def, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		/* TX2 modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		/* TX1 modulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int ltq_vrx200_pcie_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (of_device_is_big_endian(priv->dev->of_node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		regmap_update_bits(priv->rcu_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				   priv->rcu_ahb_endian_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				   priv->rcu_ahb_endian_big_endian_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				   priv->rcu_ahb_endian_big_endian_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		regmap_update_bits(priv->rcu_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				   priv->rcu_ahb_endian_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				   priv->rcu_ahb_endian_big_endian_mask, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = reset_control_assert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ret = reset_control_deassert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	ret = reset_control_deassert(priv->pcie_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		goto err_assert_phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/* Make sure PHY PLL is stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	usleep_range(20, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err_assert_phy_reset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	reset_control_assert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int ltq_vrx200_pcie_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	ret = reset_control_assert(priv->pcie_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	ret = reset_control_assert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* Enable PDI to access PCIe PHY register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ret = clk_prepare_enable(priv->pdi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	/* Configure PLL and PHY clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	ltq_vrx200_pcie_phy_common_setup(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	pcie_phy_36mhz_mode_setup(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* Enable the PCIe PHY and make PLL setting take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ret = clk_prepare_enable(priv->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		goto err_disable_pdi_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	/* Check if we are in "startup ready" status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ret = ltq_vrx200_pcie_phy_wait_for_pll(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		goto err_disable_phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	ltq_vrx200_pcie_phy_apply_workarounds(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err_disable_phy_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	clk_disable_unprepare(priv->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) err_disable_pdi_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	clk_disable_unprepare(priv->pdi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int ltq_vrx200_pcie_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	clk_disable_unprepare(priv->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	clk_disable_unprepare(priv->pdi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct phy_ops ltq_vrx200_pcie_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.init		= ltq_vrx200_pcie_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.exit		= ltq_vrx200_pcie_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.power_on	= ltq_vrx200_pcie_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.power_off	= ltq_vrx200_pcie_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 					     struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct ltq_vrx200_pcie_phy_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (args->args_count != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		dev_err(dev, "invalid number of arguments\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	mode = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	case LANTIQ_PCIE_PHY_MODE_36MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		priv->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	case LANTIQ_PCIE_PHY_MODE_25MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	case LANTIQ_PCIE_PHY_MODE_25MHZ_SSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	case LANTIQ_PCIE_PHY_MODE_36MHZ_SSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	case LANTIQ_PCIE_PHY_MODE_100MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	case LANTIQ_PCIE_PHY_MODE_100MHZ_SSC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		dev_err(dev, "PHY mode not implemented yet: %u\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		dev_err(dev, "invalid PHY mode %u\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	return priv->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		.val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		.max_register = PCIE_PHY_RX1_A_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	struct ltq_vrx200_pcie_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	priv->phy_regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (IS_ERR(priv->phy_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		return PTR_ERR(priv->phy_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 							   "lantiq,rcu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (IS_ERR(priv->rcu_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return PTR_ERR(priv->rcu_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 				       &priv->rcu_ahb_endian_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			"failed to parse the 'lantiq,rcu-endian-offset' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 				       &priv->rcu_ahb_endian_big_endian_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			"failed to parse the 'lantiq,rcu-big-endian-mask' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	priv->pdi_clk = devm_clk_get(dev, "pdi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (IS_ERR(priv->pdi_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		return PTR_ERR(priv->pdi_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	priv->phy_clk = devm_clk_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (IS_ERR(priv->phy_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		return PTR_ERR(priv->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (IS_ERR(priv->phy_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		return PTR_ERR(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	if (IS_ERR(priv->pcie_reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return PTR_ERR(priv->pcie_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	priv->phy = devm_phy_create(dev, dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 				    &ltq_vrx200_pcie_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	if (IS_ERR(priv->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	phy_set_drvdata(priv->phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	provider = devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 						 ltq_vrx200_pcie_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	{ .compatible = "lantiq,vrx200-pcie-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	{ .compatible = "lantiq,arx300-pcie-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct platform_driver ltq_vrx200_pcie_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	.probe	= ltq_vrx200_pcie_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		.name	= "ltq-vrx200-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		.of_match_table	= ltq_vrx200_pcie_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) module_platform_driver(ltq_vrx200_pcie_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_DESCRIPTION("Lantiq VRX200 and ARX300 PCIe PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_LICENSE("GPL v2");