^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Transmitter HS Pre-Emphasis Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RCU_CFG1_TX_PEE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Disconnect Threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RCU_CFG1_DIS_THR_MASK 0x00038000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RCU_CFG1_DIS_THR_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct ltq_rcu_usb2_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 hostmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 slave_endianness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 host_endianness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) bool have_ana_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct ltq_rcu_usb2_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int phy_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int ana_cfg1_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const struct ltq_rcu_usb2_bits *reg_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *phy_gate_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct reset_control *ctrl_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct reset_control *phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .hostmode = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .slave_endianness = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .host_endianness = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .have_ana_cfg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .hostmode = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .slave_endianness = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .host_endianness = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .have_ana_cfg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .hostmode = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .slave_endianness = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .host_endianness = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .have_ana_cfg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .compatible = "lantiq,ase-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .data = &xway_rcu_usb2_reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .compatible = "lantiq,danube-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .data = &xway_rcu_usb2_reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .compatible = "lantiq,xrx100-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .data = &xrx100_rcu_usb2_reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .compatible = "lantiq,xrx200-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .data = &xrx200_rcu_usb2_reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .compatible = "lantiq,xrx300-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .data = &xrx200_rcu_usb2_reg_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int ltq_rcu_usb2_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (priv->reg_bits->have_ana_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Configure core to host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_update_bits(priv->regmap, priv->phy_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BIT(priv->reg_bits->hostmode), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Select DMA endianness (Host-endian: big-endian) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) regmap_update_bits(priv->regmap, priv->phy_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BIT(priv->reg_bits->slave_endianness), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) regmap_update_bits(priv->regmap, priv->phy_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BIT(priv->reg_bits->host_endianness),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BIT(priv->reg_bits->host_endianness));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reset_control_deassert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = clk_prepare_enable(priv->phy_gate_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(dev, "failed to enable PHY gate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * at least the xrx200 usb2 phy requires some extra time to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * operational after enabling the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reset_control_assert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_disable_unprepare(priv->phy_gate_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct phy_ops ltq_rcu_usb2_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .init = ltq_rcu_usb2_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .power_on = ltq_rcu_usb2_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .power_off = ltq_rcu_usb2_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int ltq_rcu_usb2_of_parse(struct ltq_rcu_usb2_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const __be32 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) priv->reg_bits = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(dev, "Failed to lookup RCU regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) offset = of_get_address(dev->of_node, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(dev, "Failed to get RCU PHY reg offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) priv->phy_reg_offset = __be32_to_cpu(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (priv->reg_bits->have_ana_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) offset = of_get_address(dev->of_node, 1, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(dev, "Failed to get RCU ANA CFG1 reg offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) priv->ana_cfg1_reg_offset = __be32_to_cpu(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) priv->phy_gate_clk = devm_clk_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(priv->phy_gate_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(dev, "Unable to get USB phy gate clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return PTR_ERR(priv->phy_gate_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (IS_ERR(priv->ctrl_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(dev, "failed to get 'ctrl' reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return PTR_ERR(priv->ctrl_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return PTR_ERR_OR_ZERO(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ltq_rcu_usb2_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = ltq_rcu_usb2_of_parse(priv, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Reset USB core through reset controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reset_control_deassert(priv->ctrl_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reset_control_assert(priv->phy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->phy = devm_phy_create(dev, dev->of_node, <q_rcu_usb2_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (IS_ERR(priv->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) phy_set_drvdata(priv->phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dev_set_drvdata(priv->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver ltq_rcu_usb2_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .probe = ltq_rcu_usb2_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "lantiq-rcu-usb2-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .of_match_table = ltq_rcu_usb2_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) module_platform_driver(ltq_rcu_usb2_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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