^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel eMMC PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Intel, Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* eMMC phy register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EMMC_PHYCTRL0_REG 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DR_TY_MASK GENMASK(30, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DR_TY_SHIFT(x) (((x) << 28) & DR_TY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OTAPDLYENA BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OTAPDLYSEL_MASK GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OTAPDLYSEL_SHIFT(x) (((x) << 10) & OTAPDLYSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EMMC_PHYCTRL1_REG 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PDB_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PDB_SHIFT(x) (((x) << 0) & PDB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ENDLL_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ENDLL_SHIFT(x) (((x) << 7) & ENDLL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EMMC_PHYCTRL2_REG 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FRQSEL_25M 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FRQSEL_50M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FRQSEL_100M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FRQSEL_150M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FRQSEL_MASK GENMASK(24, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FRQSEL_SHIFT(x) (((x) << 22) & FRQSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EMMC_PHYSTAT_REG 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CALDONE_MASK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DLLRDY_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IS_CALDONE(x) ((x) & CALDONE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IS_DLLRDY(x) ((x) & DLLRDY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct intel_emmc_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct regmap *syscfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *emmcclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int intel_emmc_phy_power(struct phy *phy, bool on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct intel_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int caldone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int dllrdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int freqsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int ret, quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Keep phyctrl_pdb and phyctrl_endll low to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * initialization of CALIO state M/C DFFs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PDB_SHIFT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Already finish power_off above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rate = clk_get_rate(priv->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) quot = DIV_ROUND_CLOSEST(rate, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (quot > FRQSEL_150M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) freqsel = clamp_t(int, quot, FRQSEL_25M, FRQSEL_150M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * According to the user manual, calpad calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * cycle takes more than 2us without the minimal recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * value, so we may need a little margin here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PDB_SHIFT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * According to the user manual, it asks driver to wait 5us for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * calpad busy trimming. However it is documented that this value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * PVT(A.K.A process,voltage and temperature) relevant, so some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * failure cases are found which indicates we should be more tolerant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * to calpad busy trimming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) caldone, IS_CALDONE(caldone),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Set the frequency of the DLL operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FRQSEL_SHIFT(freqsel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Turn on the DLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ENDLL_SHIFT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * After enabling analog DLL circuits docs say that we need 10.2 us if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * our source clock is at 50 MHz and that lock time scales linearly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * with clock speed. If we are powering on the PHY and the card clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Hopefully we won't be running at 100 kHz, but we should still make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * sure we wait long enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * NOTE: There appear to be corner cases where the DLL seems to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * extra long to lock for reasons that aren't understood. In some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * extreme cases we've seen it take up to over 10ms (!). We'll be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * generous and give it 50ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = regmap_read_poll_timeout(priv->syscfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EMMC_PHYSTAT_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dllrdy, IS_DLLRDY(dllrdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0, 50 * USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(&phy->dev, "dllrdy failed. ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int intel_emmc_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct intel_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * We purposely get the clock here and not in probe to avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * circular dependency problem. We expect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * - PHY driver to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * - SDHCI driver to start probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * - SDHCI driver to register it's clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * - SDHCI driver to get the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * - SDHCI driver to init the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * The clock is optional, so upon any error just return it like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * any other error to user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (IS_ERR(priv->emmcclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(&phy->dev, "ERROR: getting emmcclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return PTR_ERR(priv->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int intel_emmc_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct intel_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clk_put(priv->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int intel_emmc_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct intel_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Drive impedance: 50 Ohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DR_TY_SHIFT(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(&phy->dev, "ERROR set drive-impednce-50ohm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Output tap delay: disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_err(&phy->dev, "ERROR Set output tap delay : %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Output tap delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) OTAPDLYSEL_MASK, OTAPDLYSEL_SHIFT(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&phy->dev, "ERROR: output tap dly select: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Power up eMMC phy analog blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return intel_emmc_phy_power(phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int intel_emmc_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Power down eMMC phy analog blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return intel_emmc_phy_power(phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .init = intel_emmc_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .exit = intel_emmc_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .power_on = intel_emmc_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .power_off = intel_emmc_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int intel_emmc_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct intel_emmc_phy *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Get eMMC phy (accessed via chiptop) regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (IS_ERR(priv->syscfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(dev, "failed to find syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return PTR_ERR(priv->syscfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) generic_phy = devm_phy_create(dev, np, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (IS_ERR(generic_phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return PTR_ERR(generic_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) phy_set_drvdata(generic_phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct of_device_id intel_emmc_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .compatible = "intel,lgm-emmc-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MODULE_DEVICE_TABLE(of, intel_emmc_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct platform_driver intel_emmc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .probe = intel_emmc_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "intel-emmc-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .of_match_table = intel_emmc_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_platform_driver(intel_emmc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_AUTHOR("Peter Harliman Liem <peter.harliman.liem@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DESCRIPTION("Intel eMMC PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags