^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Combo-PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019-2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIE_PHY_GEN_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCIE_PHY_CLK_PAD BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAD_DIS_CFG 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCS_XF_ATE_OVRD_IN_2 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADAPT_REQ_MSK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCS_XF_RX_ADAPT_ACK 0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RX_ADAPT_ACK_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CR_ADDR(addr, lane) (((addr) + (lane) * 0x100) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_COMBO_MODE(x) ((x) * 0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_CLK_DISABLE(x) ((x) * 0x200 + 0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define COMBO_PHY_ID(x) ((x)->parent->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PHY_ID(x) ((x)->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_100MHZ 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_156_25MHZ 156250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const unsigned long intel_iphy_clk_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CLK_100MHZ, CLK_156_25MHZ, CLK_100MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PHY_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PHY_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PHY_MAX_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Clock Register bit fields to enable clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * for ComboPhy according to the mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum intel_phy_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PHY_PCIE_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PHY_XPCS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PHY_SATA_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ComboPhy mode Register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum intel_combo_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PCIE0_PCIE1_MODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PCIE_DL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) RXAUI_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) XPCS0_XPCS1_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SATA0_SATA1_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum aggregated_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PHY_SL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PHY_DL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct intel_combo_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct intel_cbphy_iphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct intel_combo_phy *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct reset_control *app_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct intel_combo_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *cr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap *syscfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct regmap *hsiocfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 bid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct reset_control *phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct reset_control *core_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct intel_cbphy_iphy iphy[PHY_MAX_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum intel_phy_mode phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum aggregated_mode aggr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 init_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int intel_cbphy_iphy_enable(struct intel_cbphy_iphy *iphy, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Register: 0 is enable, 1 is disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = set ? 0 : mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return regmap_update_bits(cbphy->hsiocfg, REG_CLK_DISABLE(cbphy->bid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int intel_cbphy_pcie_refclk_cfg(struct intel_cbphy_iphy *iphy, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 mask = BIT(cbphy->id * 2 + iphy->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Register: 0 is enable, 1 is disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = set ? 0 : mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return regmap_update_bits(cbphy->syscfg, PAD_DIS_CFG, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void combo_phy_w32_off_mask(void __iomem *base, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg_val = readl(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) reg_val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg_val |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) writel(reg_val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int intel_cbphy_iphy_cfg(struct intel_cbphy_iphy *iphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int (*phy_cfg)(struct intel_cbphy_iphy *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = phy_cfg(iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (cbphy->aggr_mode != PHY_DL_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return phy_cfg(&cbphy->iphy[PHY_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int intel_cbphy_pcie_en_pad_refclk(struct intel_cbphy_iphy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = intel_cbphy_pcie_refclk_cfg(iphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(cbphy->dev, "Failed to enable PCIe pad refclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (cbphy->init_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PCIE_PHY_CLK_PAD, FIELD_PREP(PCIE_PHY_CLK_PAD, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Delay for stable clock PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) usleep_range(50, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int intel_cbphy_pcie_dis_pad_refclk(struct intel_cbphy_iphy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = intel_cbphy_pcie_refclk_cfg(iphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(cbphy->dev, "Failed to disable PCIe pad refclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (cbphy->init_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) combo_phy_w32_off_mask(cbphy->app_base, PCIE_PHY_GEN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PCIE_PHY_CLK_PAD, FIELD_PREP(PCIE_PHY_CLK_PAD, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int intel_cbphy_set_mode(struct intel_combo_phy *cbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum intel_combo_mode cb_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum aggregated_mode aggr = cbphy->aggr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct device *dev = cbphy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) enum intel_phy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mode = cbphy->phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case PHY_PCIE_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cb_mode = (aggr == PHY_DL_MODE) ? PCIE_DL_MODE : PCIE0_PCIE1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case PHY_XPCS_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cb_mode = (aggr == PHY_DL_MODE) ? RXAUI_MODE : XPCS0_XPCS1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) case PHY_SATA_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (aggr == PHY_DL_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "Mode:%u not support dual lane!\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) cb_mode = SATA0_SATA1_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = regmap_write(cbphy->hsiocfg, REG_COMBO_MODE(cbphy->bid), cb_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev, "Failed to set ComboPhy mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void intel_cbphy_rst_assert(struct intel_combo_phy *cbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reset_control_assert(cbphy->core_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reset_control_assert(cbphy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void intel_cbphy_rst_deassert(struct intel_combo_phy *cbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reset_control_deassert(cbphy->core_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reset_control_deassert(cbphy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Delay to ensure reset process is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int intel_cbphy_iphy_power_on(struct intel_cbphy_iphy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!cbphy->init_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = clk_prepare_enable(cbphy->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(cbphy->dev, "Clock enable failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = clk_set_rate(cbphy->core_clk, cbphy->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(cbphy->dev, "Clock freq set to %lu failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cbphy->clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) intel_cbphy_rst_assert(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) intel_cbphy_rst_deassert(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = intel_cbphy_set_mode(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = intel_cbphy_iphy_enable(iphy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(cbphy->dev, "Failed enabling PHY core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = reset_control_deassert(iphy->app_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(cbphy->dev, "PHY(%u:%u) reset deassert failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) COMBO_PHY_ID(iphy), PHY_ID(iphy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Delay to ensure reset process is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_disable_unprepare(cbphy->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int intel_cbphy_iphy_power_off(struct intel_cbphy_iphy *iphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = reset_control_assert(iphy->app_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(cbphy->dev, "PHY(%u:%u) reset assert failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) COMBO_PHY_ID(iphy), PHY_ID(iphy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = intel_cbphy_iphy_enable(iphy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(cbphy->dev, "Failed disabling PHY core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (cbphy->init_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) clk_disable_unprepare(cbphy->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) intel_cbphy_rst_assert(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int intel_cbphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mutex_lock(&cbphy->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_iphy_power_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (cbphy->phy_mode == PHY_PCIE_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_en_pad_refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cbphy->init_cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mutex_unlock(&cbphy->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int intel_cbphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mutex_lock(&cbphy->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cbphy->init_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (cbphy->phy_mode == PHY_PCIE_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_dis_pad_refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_iphy_power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mutex_unlock(&cbphy->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int intel_cbphy_calibrate(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct intel_cbphy_iphy *iphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct intel_combo_phy *cbphy = iphy->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) void __iomem *cr_base = cbphy->cr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int val, ret, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (cbphy->phy_mode != PHY_XPCS_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) id = PHY_ID(iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* trigger auto RX adaptation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ADAPT_REQ_MSK, FIELD_PREP(ADAPT_REQ_MSK, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Wait RX adaptation to finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = readl_poll_timeout(cr_base + CR_ADDR(PCS_XF_RX_ADAPT_ACK, id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) val, val & RX_ADAPT_ACK_BIT, 10, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(cbphy->dev, "RX Adaptation failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_dbg(cbphy->dev, "RX Adaptation success!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Stop RX adaptation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) combo_phy_w32_off_mask(cr_base, CR_ADDR(PCS_XF_ATE_OVRD_IN_2, id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ADAPT_REQ_MSK, FIELD_PREP(ADAPT_REQ_MSK, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int intel_cbphy_fwnode_parse(struct intel_combo_phy *cbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct device *dev = cbphy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct fwnode_handle *fwnode = dev_fwnode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct fwnode_reference_args ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cbphy->core_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (IS_ERR(cbphy->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = PTR_ERR(cbphy->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(dev, "Get clk failed:%d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cbphy->core_rst = devm_reset_control_get_optional(dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (IS_ERR(cbphy->core_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = PTR_ERR(cbphy->core_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(dev, "Get core reset control err: %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cbphy->phy_rst = devm_reset_control_get_optional(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (IS_ERR(cbphy->phy_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = PTR_ERR(cbphy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(dev, "Get PHY reset control err: %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) cbphy->iphy[0].app_rst = devm_reset_control_get_optional(dev, "iphy0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (IS_ERR(cbphy->iphy[0].app_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = PTR_ERR(cbphy->iphy[0].app_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(dev, "Get phy0 reset control err: %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) cbphy->iphy[1].app_rst = devm_reset_control_get_optional(dev, "iphy1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (IS_ERR(cbphy->iphy[1].app_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = PTR_ERR(cbphy->iphy[1].app_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(dev, "Get phy1 reset control err: %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) cbphy->app_base = devm_platform_ioremap_resource_byname(pdev, "app");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (IS_ERR(cbphy->app_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return PTR_ERR(cbphy->app_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cbphy->cr_base = devm_platform_ioremap_resource_byname(pdev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (IS_ERR(cbphy->cr_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return PTR_ERR(cbphy->cr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * syscfg and hsiocfg variables stores the handle of the registers set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * in which ComboPhy subsytem specific registers are subset. Using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * Register map framework to access the registers set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = fwnode_property_get_reference_args(fwnode, "intel,syscfg", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 1, 0, &ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) cbphy->id = ref.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cbphy->syscfg = device_node_to_regmap(to_of_node(ref.fwnode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fwnode_handle_put(ref.fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = fwnode_property_get_reference_args(fwnode, "intel,hsio", NULL, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0, &ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) cbphy->bid = ref.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) cbphy->hsiocfg = device_node_to_regmap(to_of_node(ref.fwnode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) fwnode_handle_put(ref.fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = fwnode_property_read_u32_array(fwnode, "intel,phy-mode", &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cbphy->phy_mode = PHY_PCIE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cbphy->phy_mode = PHY_SATA_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case PHY_TYPE_XPCS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) cbphy->phy_mode = PHY_XPCS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_err(dev, "Invalid PHY mode: %u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cbphy->clk_rate = intel_iphy_clk_rates[cbphy->phy_mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (fwnode_property_present(fwnode, "intel,aggregation"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cbphy->aggr_mode = PHY_DL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cbphy->aggr_mode = PHY_SL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct phy_ops intel_cbphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .init = intel_cbphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .exit = intel_cbphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .calibrate = intel_cbphy_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct phy *intel_cbphy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct intel_combo_phy *cbphy = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 iphy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (args->args_count < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(dev, "Invalid number of arguments\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) iphy_id = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (iphy_id >= PHY_MAX_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(dev, "Invalid phy instance %d\n", iphy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (cbphy->aggr_mode == PHY_DL_MODE && iphy_id == PHY_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_err(dev, "Invalid. ComboPhy is in Dual lane mode %d\n", iphy_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return cbphy->iphy[iphy_id].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int intel_cbphy_create(struct intel_combo_phy *cbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct device *dev = cbphy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct intel_cbphy_iphy *iphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) for (i = 0; i < PHY_MAX_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) iphy = &cbphy->iphy[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) iphy->parent = cbphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) iphy->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* In dual lane mode skip phy creation for the second phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (cbphy->aggr_mode == PHY_DL_MODE && iphy->id == PHY_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) iphy->phy = devm_phy_create(dev, NULL, &intel_cbphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(iphy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dev_err(dev, "PHY[%u:%u]: create PHY instance failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) COMBO_PHY_ID(iphy), PHY_ID(iphy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return PTR_ERR(iphy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) phy_set_drvdata(iphy->phy, iphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_set_drvdata(dev, cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) phy_provider = devm_of_phy_provider_register(dev, intel_cbphy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (IS_ERR(phy_provider))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_err(dev, "Register PHY provider failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int intel_cbphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct intel_combo_phy *cbphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cbphy = devm_kzalloc(dev, sizeof(*cbphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!cbphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cbphy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cbphy->init_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mutex_init(&cbphy->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = intel_cbphy_fwnode_parse(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) platform_set_drvdata(pdev, cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return intel_cbphy_create(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int intel_cbphy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct intel_combo_phy *cbphy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) intel_cbphy_rst_assert(cbphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) clk_disable_unprepare(cbphy->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct of_device_id of_intel_cbphy_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { .compatible = "intel,combo-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { .compatible = "intel,combophy-lgm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static struct platform_driver intel_cbphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .probe = intel_cbphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .remove = intel_cbphy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .name = "intel-combo-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .of_match_table = of_intel_cbphy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) module_platform_driver(intel_cbphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_DESCRIPTION("Intel Combo-phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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