^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Keem Bay eMMC PHY driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2020 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* eMMC/SD/SDIO core/phy configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_CFG_0 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SEL_DLY_TXCLK_MASK BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OTAP_DLY_ENA_MASK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OTAP_DLY_SEL_MASK GENMASK(26, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DLL_EN_MASK BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWR_DOWN_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_CFG_2 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SEL_FREQ_MASK GENMASK(12, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_STAT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CAL_DONE_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IS_CALDONE(x) ((x) & CAL_DONE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DLL_RDY_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IS_DLLRDY(x) ((x) & DLL_RDY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* From ACS_eMMC51_16nFFC_RO1100_Userguide_v1p0.pdf p17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FREQSEL_200M_170M 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FREQSEL_170M_140M 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FREQSEL_140M_110M 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FREQSEL_110M_80M 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FREQSEL_80M_50M 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct keembay_emmc_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct regmap *syscfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct clk *emmcclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct regmap_config keembay_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int keembay_emmc_phy_power(struct phy *phy, bool on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int caldone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int dllrdy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int freqsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Keep phyctrl_pdb and phyctrl_endll low to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * initialization of CALIO state M/C DFFs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FIELD_PREP(PWR_DOWN_MASK, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FIELD_PREP(DLL_EN_MASK, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_err(&phy->dev, "turn off the dll failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Already finish power off above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (mhz <= 200 && mhz >= 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) freqsel = FREQSEL_200M_170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else if (mhz <= 170 && mhz >= 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) freqsel = FREQSEL_170M_140M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else if (mhz <= 140 && mhz >= 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) freqsel = FREQSEL_140M_110M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else if (mhz <= 110 && mhz >= 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) freqsel = FREQSEL_110M_80M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else if (mhz <= 80 && mhz >= 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) freqsel = FREQSEL_80M_50M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) freqsel = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Check for EMMC clock rate*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (mhz > 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * According to the user manual, calpad calibration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * cycle takes more than 2us without the minimal recommended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * value, so we may need a little margin here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FIELD_PREP(PWR_DOWN_MASK, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * According to the user manual, it asks driver to wait 5us for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * calpad busy trimming. However it is documented that this value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * PVT(A.K.A. process, voltage and temperature) relevant, so some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * failure cases are found which indicates we should be more tolerant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * to calpad busy trimming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) caldone, IS_CALDONE(caldone),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Set the frequency of the DLL operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = regmap_update_bits(priv->syscfg, PHY_CFG_2, SEL_FREQ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FIELD_PREP(SEL_FREQ_MASK, freqsel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Turn on the DLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FIELD_PREP(DLL_EN_MASK, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * We turned on the DLL even though the rate was 0 because we the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * clock might be turned on later. ...but we can't wait for the DLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * to lock when the rate is 0 because it will never lock with no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Technically we should be checking the lock later when the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * is turned on, but for now we won't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (mhz == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * After enabling analog DLL circuits docs say that we need 10.2 us if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * our source clock is at 50 MHz and that lock time scales linearly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * with clock speed. If we are powering on the PHY and the card clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * is super slow (like 100kHz) this could take as long as 5.1 ms as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * hopefully we won't be running at 100 kHz, but we should still make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * sure we wait long enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * NOTE: There appear to be corner cases where the DLL seems to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * extra long to lock for reasons that aren't understood. In some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * extreme cases we've seen it take up to over 10ms (!). We'll be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * generous and give it 50ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dllrdy, IS_DLLRDY(dllrdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0, 50 * USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int keembay_emmc_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * We purposely get the clock here and not in probe to avoid the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * circular dependency problem. We expect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * - PHY driver to probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * - SDHCI driver to start probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * - SDHCI driver to register it's clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * - SDHCI driver to get the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * - SDHCI driver to init the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The clock is optional, so upon any error just return it like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * any other error to user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return PTR_ERR_OR_ZERO(priv->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int keembay_emmc_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clk_put(priv->emmcclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int keembay_emmc_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Delay chain based txclk: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FIELD_PREP(SEL_DLY_TXCLK_MASK, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&phy->dev, "ERROR: delay chain txclk set: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Output tap delay: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_ENA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FIELD_PREP(OTAP_DLY_ENA_MASK, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(&phy->dev, "ERROR: output tap delay set: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Output tap delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FIELD_PREP(OTAP_DLY_SEL_MASK, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(&phy->dev, "ERROR: output tap delay select: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Power up eMMC phy analog blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return keembay_emmc_phy_power(phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int keembay_emmc_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Power down eMMC phy analog blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return keembay_emmc_phy_power(phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .init = keembay_emmc_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .exit = keembay_emmc_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .power_on = keembay_emmc_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .power_off = keembay_emmc_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int keembay_emmc_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct keembay_emmc_phy *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct phy *generic_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) priv->syscfg = devm_regmap_init_mmio(dev, base, &keembay_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (IS_ERR(priv->syscfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return PTR_ERR(priv->syscfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) generic_phy = devm_phy_create(dev, np, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (IS_ERR(generic_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return dev_err_probe(dev, PTR_ERR(generic_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) phy_set_drvdata(generic_phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct of_device_id keembay_emmc_phy_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { .compatible = "intel,keembay-emmc-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_DEVICE_TABLE(of, keembay_emmc_phy_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct platform_driver keembay_emmc_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .probe = keembay_emmc_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "keembay-emmc-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .of_match_table = keembay_emmc_phy_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) module_platform_driver(keembay_emmc_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_DESCRIPTION("Intel Keem Bay eMMC PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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