^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014 Hisilicon Limited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SATA_PHY0_CTLL 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPLL_MULTIPLIER_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPLL_MULTIPLIER_MASK 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPLL_MULTIPLIER_50M 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPLL_MULTIPLIER_100M 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REF_SSP_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SSC_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REF_USE_PAD BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SATA_PORT_PHYCTL 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPEED_MODE_MASK 0x6f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HALF_RATE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_CONFIG_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GEN2_EN_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPEED_CTRL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SATA_PORT_PHYCTL1 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AMPLITUDE_MASK 0x3ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AMPLITUDE_GEN3 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AMPLITUDE_GEN3_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AMPLITUDE_GEN2 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AMPLITUDE_GEN2_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AMPLITUDE_GEN1 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AMPLITUDE_GEN1_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SATA_PORT_PHYCTL2 0x14c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PREEMPH_MASK 0x3ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PREEMPH_GEN3 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PREEMPH_GEN3_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PREEMPH_GEN2 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PREEMPH_GEN2_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PREEMPH_GEN1 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PREEMPH_GEN1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct hix5hd2_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct regmap *peri_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum phy_speed_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SPEED_MODE_GEN1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SPEED_MODE_GEN2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SPEED_MODE_GEN3 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int hix5hd2_sata_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct hix5hd2_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 val, data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (priv->peri_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = of_property_read_u32_array(phy->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "hisilicon,power-reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) &data[0], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(&phy->dev, "Fail read hisilicon,power-reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) regmap_update_bits(priv->peri_ctrl, data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) BIT(data[1]), BIT(data[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* reset phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val = readl_relaxed(priv->base + SATA_PHY0_CTLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) REF_SSP_EN | PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel_relaxed(val, priv->base + SATA_PHY0_CTLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val &= ~PHY_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writel_relaxed(val, priv->base + SATA_PHY0_CTLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val &= ~AMPLITUDE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) AMPLITUDE_GEN2 << AMPLITUDE_GEN2_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) AMPLITUDE_GEN1 << AMPLITUDE_GEN1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val &= ~PREEMPH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PREEMPH_GEN2 << PREEMPH_GEN2_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PREEMPH_GEN1 << PREEMPH_GEN1_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* ensure PHYCTRL setting takes effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val = readl_relaxed(priv->base + SATA_PORT_PHYCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val &= ~SPEED_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SPEED_MODE_GEN1 << PHY_CONFIG_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SPEED_MODE_GEN1 << GEN2_EN_SHIFT | SPEED_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val &= ~SPEED_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SPEED_MODE_GEN3 << PHY_CONFIG_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SPEED_MODE_GEN3 << GEN2_EN_SHIFT | SPEED_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val &= ~(SPEED_MODE_MASK | SPEED_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SPEED_MODE_GEN2 << PHY_CONFIG_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SPEED_MODE_GEN2 << GEN2_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct phy_ops hix5hd2_sata_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .init = hix5hd2_sata_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int hix5hd2_sata_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct hix5hd2_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) priv->base = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!priv->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->peri_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "hisilicon,peripheral-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(priv->peri_ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) priv->peri_ctrl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct of_device_id hix5hd2_sata_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {.compatible = "hisilicon,hix5hd2-sata-phy",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_DEVICE_TABLE(of, hix5hd2_sata_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct platform_driver hix5hd2_sata_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .probe = hix5hd2_sata_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "hix5hd2-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .of_match_table = hix5hd2_sata_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) module_platform_driver(hix5hd2_sata_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_AUTHOR("Jiancheng Xue <xuejiancheng@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_DESCRIPTION("HISILICON HIX5HD2 SATA PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_ALIAS("platform:hix5hd2-sata-phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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