^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * COMBPHY driver for HiSilicon STB SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Jianguo Sun <sunjianguo1@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define COMBPHY_MODE_PCIE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define COMBPHY_MODE_USB3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define COMBPHY_MODE_SATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define COMBPHY_CFG_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define COMBPHY_BYPASS_CODEC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define COMBPHY_TEST_WRITE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define COMBPHY_TEST_DATA_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define COMBPHY_TEST_DATA_MASK GENMASK(23, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define COMBPHY_TEST_ADDR_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define COMBPHY_TEST_ADDR_MASK GENMASK(16, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define COMBPHY_CLKREF_OUT_OEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct histb_combphy_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct histb_combphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct reset_control *por_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct histb_combphy_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void nano_register_write(struct histb_combphy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void __iomem *reg = priv->mmio + COMBPHY_CFG_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Set up address and data for the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val &= ~COMBPHY_TEST_ADDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val |= addr << COMBPHY_TEST_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) val &= ~COMBPHY_TEST_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) val |= data << COMBPHY_TEST_DATA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Flip strobe control to trigger the write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val &= ~COMBPHY_TEST_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) val |= COMBPHY_TEST_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int is_mode_fixed(struct histb_combphy_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return (mode->fixed != PHY_NONE) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int histb_combphy_set_mode(struct histb_combphy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct histb_combphy_mode *mode = &priv->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct regmap *syscon = priv->syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 hw_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (is_mode_fixed(mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) switch (mode->select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case PHY_TYPE_SATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) hw_sel = COMBPHY_MODE_SATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hw_sel = COMBPHY_MODE_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) hw_sel = COMBPHY_MODE_USB3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return regmap_update_bits(syscon, mode->reg, mode->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hw_sel << mode->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int histb_combphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct histb_combphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = histb_combphy_set_mode(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Clear bypass bit to enable encoding/decoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val = readl(priv->mmio + COMBPHY_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val &= ~COMBPHY_BYPASS_CODEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(val, priv->mmio + COMBPHY_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = clk_prepare_enable(priv->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) reset_control_deassert(priv->por_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Enable EP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val = readl(priv->mmio + COMBPHY_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= COMBPHY_CLKREF_OUT_OEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writel(val, priv->mmio + COMBPHY_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Need to wait for EP clock stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mdelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Configure nano phy registers as suggested by vendor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) nano_register_write(priv, 0x1, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) nano_register_write(priv, 0xc, 0x9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) nano_register_write(priv, 0x1a, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int histb_combphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct histb_combphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Disable EP clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val = readl(priv->mmio + COMBPHY_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val &= ~COMBPHY_CLKREF_OUT_OEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(val, priv->mmio + COMBPHY_CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reset_control_assert(priv->por_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clk_disable_unprepare(priv->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct phy_ops histb_combphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .init = histb_combphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .exit = histb_combphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct phy *histb_combphy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct histb_combphy_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct histb_combphy_mode *mode = &priv->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (args->args_count < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dev_err(dev, "invalid number of arguments\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mode->select = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (mode->select < PHY_TYPE_SATA || mode->select > PHY_TYPE_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_err(dev, "invalid phy mode select argument\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (is_mode_fixed(mode) && mode->select != mode->fixed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(dev, "mode select %d mismatch fixed phy mode %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mode->select, mode->fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return priv->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int histb_combphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct histb_combphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct histb_combphy_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 vals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) priv->mmio = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (IS_ERR(priv->mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = PTR_ERR(priv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) priv->syscon = syscon_node_to_regmap(np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(priv->syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(dev, "failed to find peri_ctrl syscon regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PTR_ERR(priv->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mode = &priv->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mode->fixed = PHY_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = of_property_read_u32(np, "hisilicon,fixed-mode", &mode->fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_dbg(dev, "found fixed phy mode %d\n", mode->fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = of_property_read_u32_array(np, "hisilicon,mode-select-bits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vals, ARRAY_SIZE(vals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (is_mode_fixed(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(dev, "found select bits for fixed mode phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mode->reg = vals[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mode->shift = vals[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mode->mask = vals[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_dbg(dev, "found mode select bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!is_mode_fixed(mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "no valid select bits found for non-fixed phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->ref_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(priv->ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dev, "failed to find ref clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return PTR_ERR(priv->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) priv->por_rst = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (IS_ERR(priv->por_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(dev, "failed to get poweron reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return PTR_ERR(priv->por_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) priv->phy = devm_phy_create(dev, NULL, &histb_combphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (IS_ERR(priv->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(dev, "failed to create combphy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) phy_set_drvdata(priv->phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) phy_provider = devm_of_phy_provider_register(dev, histb_combphy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct of_device_id histb_combphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .compatible = "hisilicon,hi3798cv200-combphy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DEVICE_TABLE(of, histb_combphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct platform_driver histb_combphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .probe = histb_combphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "combphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .of_match_table = histb_combphy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) module_platform_driver(histb_combphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DESCRIPTION("HiSilicon STB COMBPHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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