^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HiSilicon INNO USB2 PHY Driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INNO_PHY_PORT_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REF_CLK_STABLE_TIME 100 /* unit:us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UTMI_CLK_STABLE_TIME 200 /* unit:us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEST_CLK_STABLE_TIME 2 /* unit:ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_CLK_STABLE_TIME 2 /* unit:ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define POR_RST_COMPLETE_TIME 300 /* unit:us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHY_TEST_DATA GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_TEST_ADDR GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PHY_TEST_PORT GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_TEST_WREN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHY_TEST_CLK BIT(22) /* rising edge active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_TEST_RST BIT(23) /* low active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PHY_CLK_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct hisi_inno_phy_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct reset_control *utmi_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct hisi_inno_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct hisi_inno_phy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk *ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct reset_control *por_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 port, u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *reg = priv->mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) val = (data & PHY_TEST_DATA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ((addr << 8) & PHY_TEST_ADDR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ((port << 16) & PHY_TEST_PORT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PHY_TEST_WREN | PHY_TEST_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) val |= PHY_TEST_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) val &= ~PHY_TEST_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* The phy clk is controlled by the port0 register 0x06. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) msleep(PHY_CLK_STABLE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int hisi_inno_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct hisi_inno_phy_priv *priv = port->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = clk_prepare_enable(priv->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) udelay(REF_CLK_STABLE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reset_control_deassert(priv->por_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) udelay(POR_RST_COMPLETE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Set up phy registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hisi_inno_phy_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reset_control_deassert(port->utmi_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) udelay(UTMI_RST_COMPLETE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int hisi_inno_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct hisi_inno_phy_priv *priv = port->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reset_control_assert(port->utmi_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reset_control_assert(priv->por_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_disable_unprepare(priv->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct phy_ops hisi_inno_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .init = hisi_inno_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .exit = hisi_inno_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int hisi_inno_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct hisi_inno_phy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) priv->mmio = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (IS_ERR(priv->mmio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = PTR_ERR(priv->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) priv->ref_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (IS_ERR(priv->ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PTR_ERR(priv->ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) priv->por_rst = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (IS_ERR(priv->por_rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return PTR_ERR(priv->por_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rst = of_reset_control_get_exclusive(child, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (IS_ERR(rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) priv->ports[i].utmi_rst = rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) priv->ports[i].priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) phy = devm_phy_create(dev, child, &hisi_inno_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) phy_set_bus_width(phy, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) phy_set_drvdata(phy, &priv->ports[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (i > INNO_PHY_PORT_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_warn(dev, "Support %d ports in maximum\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return PTR_ERR_OR_ZERO(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct of_device_id hisi_inno_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .compatible = "hisilicon,inno-usb2-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .compatible = "hisilicon,hi3798cv200-usb2-phy", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct platform_driver hisi_inno_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .probe = hisi_inno_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "hisi-inno-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .of_match_table = hisi_inno_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) module_platform_driver(hisi_inno_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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