^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Phy provider for USB 3.0 controller on HiSilicon 3660 platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2018 Hilisicon Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.huawei.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Authors: Yu Chen <chenyu56@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PERI_CRG_CLK_EN4 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PERI_CRG_CLK_DIS4 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GT_CLK_USB3OTG_REF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GT_ACLK_USB3OTG BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PERI_CRG_RSTEN4 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PERI_CRG_RSTDIS4 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IP_RST_USB3OTGPHY_POR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IP_RST_USB3OTG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PERI_CRG_ISODIS 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USB_REFCLK_ISO_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCTRL_PERI_CTRL3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCTRL_PERI_CTRL3_MSK_START 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USB_TCXO_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCTRL_PERI_CTRL24 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC_CLK_USB3PHY_3MUX1_SEL BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USBOTG3_CTRL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC_USB3PHY_ABB_GT_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USBOTG3_CTRL2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USBOTG3CTRL2_POWERDOWN_HSP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USBOTG3CTRL2_POWERDOWN_SSP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USBOTG3_CTRL3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USBOTG3_CTRL3_VBUSVLDEXT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USBOTG3_CTRL3_VBUSVLDEXTSEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USBOTG3_CTRL4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USBOTG3_CTRL7 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REF_SSP_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* This value config the default txtune parameter of the usb 2.0 phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HI3660_USB_DEFAULT_PHY_PARAM 0x1c466e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct hi3660_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct regmap *peri_crg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regmap *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct regmap *otg_bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 eye_diagram_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int hi3660_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct hi3660_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* usb refclk iso disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = regmap_write(priv->peri_crg, PERI_CRG_ISODIS, USB_REFCLK_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* enable usb_tcxo_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) val = USB_TCXO_EN | (USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* assert phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val = IP_RST_USB3OTGPHY_POR | IP_RST_USB3OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = regmap_write(priv->peri_crg, PERI_CRG_RSTEN4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* enable phy ref clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = SC_USB3PHY_ABB_GT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL0, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val = REF_SSP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL7, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* exit from IDDQ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mask = USBOTG3CTRL2_POWERDOWN_HSP | USBOTG3CTRL2_POWERDOWN_SSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL2, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* delay for exit from IDDQ mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) usleep_range(100, 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* deassert phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val = IP_RST_USB3OTGPHY_POR | IP_RST_USB3OTG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = regmap_write(priv->peri_crg, PERI_CRG_RSTDIS4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* delay for phy deasserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) usleep_range(10000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* fake vbus valid signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val = USBOTG3_CTRL3_VBUSVLDEXT | USBOTG3_CTRL3_VBUSVLDEXTSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mask = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = regmap_update_bits(priv->otg_bc, USBOTG3_CTRL3, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* delay for vbus valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) usleep_range(100, 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = regmap_write(priv->otg_bc, USBOTG3_CTRL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) priv->eye_diagram_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(priv->dev, "failed to init phy ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int hi3660_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct hi3660_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* assert phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val = IP_RST_USB3OTGPHY_POR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = regmap_write(priv->peri_crg, PERI_CRG_RSTEN4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* disable usb_tcxo_en */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = USB_TCXO_EN << PCTRL_PERI_CTRL3_MSK_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = regmap_write(priv->pctrl, PCTRL_PERI_CTRL3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(priv->dev, "failed to exit phy ret: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct phy_ops hi3660_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .init = hi3660_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .exit = hi3660_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int hi3660_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct hi3660_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) priv->peri_crg = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "hisilicon,pericrg-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (IS_ERR(priv->peri_crg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(dev, "no hisilicon,pericrg-syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return PTR_ERR(priv->peri_crg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) priv->pctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "hisilicon,pctrl-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(priv->pctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, "no hisilicon,pctrl-syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return PTR_ERR(priv->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* node of hi3660 phy is a sub-node of usb3_otg_bc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) priv->otg_bc = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (IS_ERR(priv->otg_bc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(dev, "no hisilicon,usb3-otg-bc-syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return PTR_ERR(priv->otg_bc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (of_property_read_u32(dev->of_node, "hisilicon,eye-diagram-param",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &(priv->eye_diagram_param)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) priv->eye_diagram_param = HI3660_USB_DEFAULT_PHY_PARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) phy = devm_phy_create(dev, NULL, &hi3660_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ERR(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct of_device_id hi3660_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {.compatible = "hisilicon,hi3660-usb-phy",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MODULE_DEVICE_TABLE(of, hi3660_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct platform_driver hi3660_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .probe = hi3660_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .name = "hi3660-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .of_match_table = hi3660_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) module_platform_driver(hi3660_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_AUTHOR("Yu Chen <chenyu56@huawei.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DESCRIPTION("Hilisicon Hi3660 USB3 PHY Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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