^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2017 NXP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PHY_CTRL0 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PHY_CTRL0_REF_SSP_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PHY_CTRL0_FSEL_MASK GENMASK(10, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PHY_CTRL0_FSEL_24M 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_CTRL1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_CTRL1_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PHY_CTRL1_COMMONONN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PHY_CTRL1_ATERESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHY_CTRL1_VDATSRCENB0 BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PHY_CTRL1_VDATDETENB0 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PHY_CTRL2 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PHY_CTRL2_TXENABLEN0 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PHY_CTRL2_OTG_DISABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PHY_CTRL6 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PHY_CTRL6_ALT_CLK_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PHY_CTRL6_ALT_CLK_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct imx8mq_usb_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regulator *vbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int imx8mq_usb_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) value = readl(imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PHY_CTRL1_COMMONONN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) writel(value, imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) value = readl(imx_phy->base + PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) value |= PHY_CTRL0_REF_SSP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) writel(value, imx_phy->base + PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) value = readl(imx_phy->base + PHY_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) value |= PHY_CTRL2_TXENABLEN0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(value, imx_phy->base + PHY_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) value = readl(imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel(value, imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int imx8mp_usb_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* USB3.0 PHY signal fsel for 24M ref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) value = readl(imx_phy->base + PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) value &= ~PHY_CTRL0_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel(value, imx_phy->base + PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Disable alt_clk_en and use internal MPLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) value = readl(imx_phy->base + PHY_CTRL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(value, imx_phy->base + PHY_CTRL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) value = readl(imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(value, imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) value = readl(imx_phy->base + PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) value |= PHY_CTRL0_REF_SSP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(value, imx_phy->base + PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) value = readl(imx_phy->base + PHY_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(value, imx_phy->base + PHY_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) value = readl(imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel(value, imx_phy->base + PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int imx8mq_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = regulator_enable(imx_phy->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return clk_prepare_enable(imx_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int imx8mq_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct imx8mq_usb_phy *imx_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_disable_unprepare(imx_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regulator_disable(imx_phy->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct phy_ops imx8mq_usb_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .init = imx8mq_usb_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .power_on = imx8mq_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .power_off = imx8mq_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct phy_ops imx8mp_usb_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .init = imx8mp_usb_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .power_on = imx8mq_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .power_off = imx8mq_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct of_device_id imx8mq_usb_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {.compatible = "fsl,imx8mq-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .data = &imx8mq_usb_phy_ops,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {.compatible = "fsl,imx8mp-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .data = &imx8mp_usb_phy_ops,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int imx8mq_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct imx8mq_usb_phy *imx_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct phy_ops *phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) imx_phy = devm_kzalloc(dev, sizeof(*imx_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!imx_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) imx_phy->clk = devm_clk_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(imx_phy->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(dev, "failed to get imx8mq usb phy clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return PTR_ERR(imx_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) imx_phy->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (IS_ERR(imx_phy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return PTR_ERR(imx_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) phy_ops = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!phy_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) imx_phy->phy = devm_phy_create(dev, NULL, phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (IS_ERR(imx_phy->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return PTR_ERR(imx_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) imx_phy->vbus = devm_regulator_get(dev, "vbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(imx_phy->vbus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return PTR_ERR(imx_phy->vbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) phy_set_drvdata(imx_phy->phy, imx_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct platform_driver imx8mq_usb_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .probe = imx8mq_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .name = "imx8mq-usb-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .of_match_table = imx8mq_usb_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) module_platform_driver(imx8mq_usb_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_DESCRIPTION("FSL IMX8MQ USB PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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