^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017,2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2019 Purism SPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* DPHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DPHY_PD_DPHY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DPHY_M_PRG_HS_PREPARE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DPHY_MC_PRG_HS_PREPARE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DPHY_M_PRG_HS_ZERO 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DPHY_MC_PRG_HS_ZERO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DPHY_M_PRG_HS_TRAIL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPHY_MC_PRG_HS_TRAIL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DPHY_PD_PLL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DPHY_TST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPHY_CN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPHY_CM 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DPHY_CO 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPHY_LOCK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DPHY_LOCK_BYP 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DPHY_REG_BYPASS_PLL 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MBPS(x) ((x) * 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DATA_RATE_MAX_SPEED MBPS(1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DATA_RATE_MIN_SPEED MBPS(80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLL_LOCK_SLEEP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLL_LOCK_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CN_BUF 0xcb7a89c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CO_BUF 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CM(x) ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ((x) < 32) ? 0xe0 | ((x) - 16) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ((x) < 64) ? 0xc0 | ((x) - 32) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ((x) < 128) ? 0x80 | ((x) - 64) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ((x) - 128))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* PHY power on is active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PWR_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PWR_OFF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum mixel_dphy_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MIXEL_IMX8MQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mixel_dphy_devdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 reg_tx_rcal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 reg_auto_pd_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 reg_rxlprp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 reg_rxcdrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 reg_rxhs_settle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [MIXEL_IMX8MQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .reg_tx_rcal = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .reg_auto_pd_en = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .reg_rxlprp = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .reg_rxcdrp = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .reg_rxhs_settle = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct mixel_dphy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* DPHY PLL parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 cn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 co;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* DPHY register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 mc_prg_hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 m_prg_hs_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 mc_prg_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 m_prg_hs_zero;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 mc_prg_hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 m_prg_hs_trail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 rxhs_settle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct mixel_dphy_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mixel_dphy_cfg cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk *phy_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct mixel_dphy_devdata *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct regmap_config mixel_dphy_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .max_register = DPHY_REG_BYPASS_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int phy_write(struct phy *phy, u32 value, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = regmap_write(priv->regmap, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Find a ratio close to the desired one using continued fraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * approximation ending either at exact match or maximum allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * nominator, denominator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void get_best_ratio(u32 *pnum, u32 *pdenom, u32 max_n, u32 max_d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 a = *pnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 b = *pdenom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 n[] = {0, 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 d[] = {1, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 whole;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) while (b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) i ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) whole = a / b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) n[i] += (n[i ^ 1] * whole);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) d[i] += (d[i ^ 1] * whole);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if ((n[i] > max_n) || (d[i] > max_d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) i ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) c = a - (b * whole);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) a = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) b = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *pnum = n[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *pdenom = d[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int mixel_dphy_config_from_opts(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct phy_configure_opts_mipi_dphy *dphy_opts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct mixel_dphy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 lp_t, numerator, denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) numerator = dphy_opts->hs_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) denominator = ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) get_best_ratio(&numerator, &denominator, 255, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!numerator || !denominator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) numerator, denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dphy_opts->hs_clk_rate, ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) while ((numerator < 16) && (denominator <= 128)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) numerator <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) denominator <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * CM ranges between 16 and 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * CN ranges between 1 and 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * CO is power of 2: 1, 2, 4, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) i = __ffs(denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (i > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) cfg->cn = denominator >> i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cfg->co = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cfg->cm = numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (cfg->cm < 16 || cfg->cm > 255 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cfg->cn < 1 || cfg->cn > 32 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cfg->co < 1 || cfg->co > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cfg->cm, cfg->cn, cfg->co);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ~ %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dphy_opts->hs_clk_rate, ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) numerator, denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(&phy->dev, "hs_clk/ref_clk=%ld/%ld ~ %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dphy_opts->hs_clk_rate, ref_clk, numerator, denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* LP clock period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) tmp = 1000000000000LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) do_div(tmp, dphy_opts->lp_clk_rate); /* ps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (tmp > ULONG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) lp_t = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_dbg(&phy->dev, "LP clock %lu, period: %u ps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dphy_opts->lp_clk_rate, lp_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* hs_prepare: in lp clock periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (2 * dphy_opts->hs_prepare > 5 * lp_t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "hs_prepare (%u) > 2.5 * lp clock period (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dphy_opts->hs_prepare, lp_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* 00: lp_t, 01: 1.5 * lp_t, 10: 2 * lp_t, 11: 2.5 * lp_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (dphy_opts->hs_prepare < lp_t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) tmp = 2 * (dphy_opts->hs_prepare - lp_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) do_div(tmp, lp_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) n = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) cfg->m_prg_hs_prepare = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* clk_prepare: in lp clock periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (2 * dphy_opts->clk_prepare > 3 * lp_t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(&phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "clk_prepare (%u) > 1.5 * lp clock period (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dphy_opts->clk_prepare, lp_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 00: lp_t, 01: 1.5 * lp_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* hs_zero: formula from NXP BSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) n = (144 * (dphy_opts->hs_clk_rate / 1000000) - 47500) / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cfg->m_prg_hs_zero = n < 1 ? 1 : n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* clk_zero: formula from NXP BSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) n = (34 * (dphy_opts->hs_clk_rate / 1000000) - 2500) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) cfg->mc_prg_hs_zero = n < 1 ? 1 : n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* clk_trail, hs_trail: formula from NXP BSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) n = (103 * (dphy_opts->hs_clk_rate / 1000000) + 10000) / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (n > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) n = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (n < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) n = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cfg->m_prg_hs_trail = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cfg->mc_prg_hs_trail = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* rxhs_settle: formula from NXP BSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (dphy_opts->hs_clk_rate < MBPS(80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) cfg->rxhs_settle = 0x0d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else if (dphy_opts->hs_clk_rate < MBPS(90))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cfg->rxhs_settle = 0x0c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) else if (dphy_opts->hs_clk_rate < MBPS(125))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cfg->rxhs_settle = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else if (dphy_opts->hs_clk_rate < MBPS(150))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cfg->rxhs_settle = 0x0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else if (dphy_opts->hs_clk_rate < MBPS(225))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) cfg->rxhs_settle = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else if (dphy_opts->hs_clk_rate < MBPS(500))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cfg->rxhs_settle = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cfg->rxhs_settle = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_dbg(&phy->dev, "phy_config: %u %u %u %u %u %u %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cfg->m_prg_hs_prepare, cfg->mc_prg_hs_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) cfg->m_prg_hs_zero, cfg->mc_prg_hs_zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) cfg->m_prg_hs_trail, cfg->mc_prg_hs_trail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cfg->rxhs_settle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void mixel_phy_set_hs_timings(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mixel_dphy_set_pll_params(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (priv->cfg.cm < 16 || priv->cfg.cm > 255 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) priv->cfg.cn < 1 || priv->cfg.cn > 32 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) priv->cfg.co < 1 || priv->cfg.co > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(&phy->dev, "Invalid CM/CN/CO values! (%u/%u/%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) priv->cfg.cm, priv->cfg.cn, priv->cfg.co);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(&phy->dev, "Using CM:%u CN:%u CO:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) priv->cfg.cm, priv->cfg.cn, priv->cfg.co);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) phy_write(phy, CM(priv->cfg.cm), DPHY_CM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) phy_write(phy, CN(priv->cfg.cn), DPHY_CN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) phy_write(phy, CO(priv->cfg.co), DPHY_CO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int mixel_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct mixel_dphy_cfg cfg = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Update the configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) memcpy(&priv->cfg, &cfg, sizeof(struct mixel_dphy_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) phy_write(phy, 0x00, DPHY_LOCK_BYP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) phy_write(phy, 0x01, priv->devdata->reg_tx_rcal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) phy_write(phy, 0x00, priv->devdata->reg_auto_pd_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) phy_write(phy, 0x02, priv->devdata->reg_rxlprp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) phy_write(phy, 0x02, priv->devdata->reg_rxcdrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) phy_write(phy, 0x25, DPHY_TST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mixel_phy_set_hs_timings(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = mixel_dphy_set_pll_params(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int mixel_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct mixel_dphy_cfg cfg = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (mode != PHY_MODE_MIPI_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int mixel_dphy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) phy_write(phy, PWR_OFF, DPHY_PD_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int mixel_dphy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) phy_write(phy, 0, DPHY_CM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) phy_write(phy, 0, DPHY_CN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) phy_write(phy, 0, DPHY_CO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int mixel_dphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = clk_prepare_enable(priv->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) phy_write(phy, PWR_ON, DPHY_PD_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = regmap_read_poll_timeout(priv->regmap, DPHY_LOCK, locked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) locked, PLL_LOCK_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PLL_LOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto clock_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) phy_write(phy, PWR_ON, DPHY_PD_DPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) clock_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clk_disable_unprepare(priv->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int mixel_dphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) phy_write(phy, PWR_OFF, DPHY_PD_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) clk_disable_unprepare(priv->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct phy_ops mixel_dphy_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .init = mixel_dphy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .exit = mixel_dphy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .power_on = mixel_dphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .power_off = mixel_dphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .configure = mixel_dphy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .validate = mixel_dphy_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct of_device_id mixel_dphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .compatible = "fsl,imx8mq-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .data = &mixel_dphy_devdata[MIXEL_IMX8MQ] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_DEVICE_TABLE(of, mixel_dphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int mixel_dphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct mixel_dphy_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) priv->devdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!priv->devdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &mixel_dphy_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_err(dev, "Couldn't create the DPHY regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) priv->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (IS_ERR(priv->phy_ref_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(dev, "No phy_ref clock found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return PTR_ERR(priv->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(dev, "phy_ref clock rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) clk_get_rate(priv->phy_ref_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) phy = devm_phy_create(dev, np, &mixel_dphy_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(dev, "Failed to create phy %ld\n", PTR_ERR(phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) phy_set_drvdata(phy, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static struct platform_driver mixel_dphy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .probe = mixel_dphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .name = "mixel-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .of_match_table = mixel_dphy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) module_platform_driver(mixel_dphy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_AUTHOR("NXP Semiconductor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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