^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cadence Torrent SD0801 PHY driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2018 Cadence Design Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REF_CLK_19_2MHz 19200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REF_CLK_25MHz 25000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAX_NUM_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NUM_SSC_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NUM_PHY_TYPE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define POLL_TIMEOUT_US 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLL_LOCK_TIMEOUT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TORRENT_COMMON_CDB_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ((0x4000 << (block_offset)) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (((ln) << 9) << (reg_offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ((0x8000 << (block_offset)) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (((ln) << 9) << (reg_offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (0xC000 << (block_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (0xE000 << (block_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TORRENT_DPTX_PHY_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * register offsets from DPTX PHY register block base (i.e MHDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * register base + 0x30a00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PHY_AUX_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PHY_RESET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PMA_TX_ELEC_IDLE_MASK 0xF0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PMA_TX_ELEC_IDLE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PHY_L00_RESET_N_MASK 0x01U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PHY_PMA_XCVR_PLLCLK_EN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_POWER_STATE_LN_0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_POWER_STATE_LN_1 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_POWER_STATE_LN_2 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_POWER_STATE_LN_3 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PHY_PMA_CMN_READY 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * register offsets from SD0801 PHY register block base (i.e MHDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * register base + 0x500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CMN_SSM_BANDGAP_TMR 0x0021U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMN_SSM_BIAS_TMR 0x0022U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CMN_PLLSM1_PLLPRE_TMR 0x0032U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMN_BGCAL_INIT_TMR 0x0064U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMN_BGCAL_ITER_TMR 0x0065U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMN_IBCAL_INIT_TMR 0x0074U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMN_PLL0_VCOCAL_TCTRL 0x0082U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMN_PLL0_INTDIV_M0 0x0090U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMN_PLL0_FRACDIVL_M0 0x0091U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CMN_PLL0_FRACDIVH_M0 0x0092U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMN_PLL0_HIGH_THR_M0 0x0093U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMN_PLL0_DSM_DIAG_M0 0x0094U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CMN_PLL0_SS_CTRL1_M0 0x0098U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CMN_PLL0_SS_CTRL2_M0 0x0099U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CMN_PLL0_SS_CTRL3_M0 0x009AU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CMN_PLL0_SS_CTRL4_M0 0x009BU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CMN_PLL0_LOCK_REFCNT_START 0x009CU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMN_PLL0_INTDIV_M1 0x00A0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CMN_PLL0_FRACDIVH_M1 0x00A2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CMN_PLL0_HIGH_THR_M1 0x00A3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMN_PLL0_DSM_DIAG_M1 0x00A4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CMN_PLL0_SS_CTRL1_M1 0x00A8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CMN_PLL0_SS_CTRL2_M1 0x00A9U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CMN_PLL0_SS_CTRL3_M1 0x00AAU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CMN_PLL0_SS_CTRL4_M1 0x00ABU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CMN_PLL1_INTDIV_M0 0x00D0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CMN_PLL1_FRACDIVL_M0 0x00D1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CMN_PLL1_FRACDIVH_M0 0x00D2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CMN_PLL1_HIGH_THR_M0 0x00D3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CMN_PLL1_DSM_DIAG_M0 0x00D4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CMN_PLL1_SS_CTRL1_M0 0x00D8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMN_PLL1_SS_CTRL2_M0 0x00D9U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CMN_PLL1_SS_CTRL3_M0 0x00DAU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CMN_PLL1_SS_CTRL4_M0 0x00DBU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMN_TXPUCAL_TUNE 0x0103U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CMN_TXPUCAL_INIT_TMR 0x0104U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMN_TXPUCAL_ITER_TMR 0x0105U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CMN_TXPDCAL_TUNE 0x010BU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMN_TXPDCAL_INIT_TMR 0x010CU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CMN_TXPDCAL_ITER_TMR 0x010DU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CMN_RXCAL_INIT_TMR 0x0114U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMN_RXCAL_ITER_TMR 0x0115U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CMN_SD_CAL_INIT_TMR 0x0124U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMN_SD_CAL_ITER_TMR 0x0125U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMN_SD_CAL_REFTIM_START 0x0126U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMN_SD_CAL_PLLCNT_START 0x0128U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CMN_DIAG_BIAS_OVRD1 0x01E1U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* PMA TX Lane registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TX_TXCC_CTRL 0x0040U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TX_TXCC_CPOST_MULT_00 0x004CU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TX_TXCC_CPOST_MULT_01 0x004DU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TX_TXCC_MGNFS_MULT_000 0x0050U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRV_DIAG_TX_DRV 0x00C6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define XCVR_DIAG_HSCLK_SEL 0x00E6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define XCVR_DIAG_HSCLK_DIV 0x00E7U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define XCVR_DIAG_BIDI_CTRL 0x00EAU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define XCVR_DIAG_PSC_OVRD 0x00EBU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TX_PSC_A0 0x0100U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TX_PSC_A1 0x0101U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TX_PSC_A2 0x0102U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TX_PSC_A3 0x0103U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TX_RCVDET_ST_TMR 0x0123U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TX_DIAG_ACYA 0x01E7U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TX_DIAG_ACYA_HBDC_MASK 0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* PMA RX Lane registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RX_PSC_A0 0x0000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RX_PSC_A1 0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RX_PSC_A2 0x0002U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RX_PSC_A3 0x0003U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RX_PSC_CAL 0x0006U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RX_CDRLF_CNFG 0x0080U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define RX_CDRLF_CNFG3 0x0082U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define RX_SIGDET_HL_FILT_TMR 0x0090U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RX_REE_GCSM1_CTRL 0x0108U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RX_REE_GCSM1_EQENM_PH1 0x0109U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RX_REE_GCSM1_EQENM_PH2 0x010AU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RX_REE_GCSM2_CTRL 0x0110U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RX_REE_PERGCSM_CTRL 0x0118U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RX_REE_ATTEN_THR 0x0149U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RX_REE_TAP1_CLIP 0x0171U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RX_REE_TAP2TON_CLIP 0x0172U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RX_REE_SMGM_CTRL1 0x0177U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RX_REE_SMGM_CTRL2 0x0178U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RX_DIAG_DFE_CTRL 0x01E0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RX_DIAG_NQST_CTRL 0x01E5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RX_DIAG_SIGDET_TUNE 0x01E8U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RX_DIAG_PI_RATE 0x01F4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RX_DIAG_PI_CAP 0x01F5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RX_DIAG_ACYA 0x01FFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* PHY PCS common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PHY_PLL_CFG 0x000EU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* PHY PMA common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PHY_PMA_CMN_CTRL1 0x0000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PHY_PMA_CMN_CTRL2 0x0001U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PHY_PMA_PLL_RAW_CTRL 0x0003U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct reg_field phy_pll_cfg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) REG_FIELD(PHY_PLL_CFG, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct reg_field phy_pma_cmn_ctrl_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct reg_field phy_pma_cmn_ctrl_2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct reg_field phy_pma_pll_raw_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct reg_field phy_reset_ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) REG_FIELD(PHY_RESET, 8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum cdns_torrent_phy_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) TYPE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) TYPE_DP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) TYPE_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TYPE_SGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) TYPE_QSGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) TYPE_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) enum cdns_torrent_ssc_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) NO_SSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EXTERNAL_SSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) INTERNAL_SSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct cdns_torrent_inst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 mlane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) enum cdns_torrent_phy_type phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct reset_control *lnk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum cdns_torrent_ssc_mode ssc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct cdns_torrent_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void __iomem *base; /* DPTX registers base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void __iomem *sd_base; /* SD0801 registers base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct reset_control *phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct reset_control *apb_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long ref_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct cdns_torrent_inst phys[MAX_NUM_LANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int nsubnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct cdns_torrent_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct regmap *regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct regmap *regmap_phy_pcs_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct regmap *regmap_phy_pma_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct regmap *regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct regmap_field *phy_pll_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct regmap_field *phy_pma_cmn_ctrl_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct regmap_field *phy_pma_cmn_ctrl_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct regmap_field *phy_pma_pll_raw_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct regmap_field *phy_reset_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum phy_powerstate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) POWERSTATE_A0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Powerstate A1 is unused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) POWERSTATE_A2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) POWERSTATE_A3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int cdns_torrent_phy_init(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int cdns_torrent_dp_init(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct cdns_torrent_inst *inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 rate, bool ssc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 rate, bool ssc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned int lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 rate, u32 num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int cdns_torrent_dp_configure(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) union phy_configure_opts *opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 num_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) enum phy_powerstate powerstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int cdns_torrent_phy_on(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int cdns_torrent_phy_off(struct phy *phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct phy_ops cdns_torrent_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .init = cdns_torrent_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .configure = cdns_torrent_dp_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .power_on = cdns_torrent_phy_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .power_off = cdns_torrent_phy_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct cdns_reg_pairs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct cdns_torrent_vals {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct cdns_reg_pairs *reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct cdns_torrent_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 block_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [NUM_SSC_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [NUM_SSC_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [NUM_SSC_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [NUM_SSC_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [NUM_SSC_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [NUM_SSC_MODE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct cdns_regmap_cdb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u8 reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct cdns_regmap_cdb_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 offset = reg << ctx->reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writew(val, ctx->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct cdns_regmap_cdb_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 offset = reg << ctx->reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *val = readw(ctx->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int cdns_regmap_dptx_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct cdns_regmap_cdb_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 offset = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) writel(val, ctx->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int cdns_regmap_dptx_read(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct cdns_regmap_cdb_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 offset = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *val = readl(ctx->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "torrent_tx_lane" n "_cdb", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .reg_stride = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .fast_io = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .reg_write = cdns_regmap_write, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .reg_read = cdns_regmap_read, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "torrent_rx_lane" n "_cdb", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .reg_stride = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .fast_io = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .reg_write = cdns_regmap_write, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .reg_read = cdns_regmap_read, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct regmap_config cdns_torrent_common_cdb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "torrent_common_cdb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .reg_write = cdns_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .reg_read = cdns_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "torrent_phy_pcs_cmn_cdb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .reg_write = cdns_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .reg_read = cdns_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = "torrent_phy_pma_cmn_cdb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .reg_write = cdns_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .reg_read = cdns_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct regmap_config cdns_torrent_dptx_phy_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .name = "torrent_dptx_phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .reg_write = cdns_regmap_dptx_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .reg_read = cdns_regmap_dptx_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* PHY mmr access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regmap_write(regmap, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) regmap_read(regmap, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* DPTX mmr access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) regmap_write(regmap, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) regmap_read(regmap, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Structure used to store values of PHY registers for voltage-related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * coefficients, for particular voltage swing and pre-emphasis level. Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * are shared across all physical lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct coefficients {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Value of DRV_DIAG_TX_DRV register to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u16 diag_tx_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u16 mgnfs_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Value of TX_TXCC_CPOST_MULT_00 register to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u16 cpost_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Array consists of values of voltage-related registers for sd0801 PHY. A value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * of 0xFFFF is a placeholder for invalid combination, and will never be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct coefficients vltg_coeff[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* voltage swing 0, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .cpost_mult = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .cpost_mult = 0x0014},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .cpost_mult = 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .cpost_mult = 0x002A}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* voltage swing 1, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .cpost_mult = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .cpost_mult = 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .cpost_mult = 0x001F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .cpost_mult = 0xFFFF}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* voltage swing 2, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .cpost_mult = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .cpost_mult = 0x0013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .cpost_mult = 0xFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .cpost_mult = 0xFFFF}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* voltage swing 3, pre-emphasis 0->3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .cpost_mult = 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .cpost_mult = 0xFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .cpost_mult = 0xFFFF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .cpost_mult = 0xFFFF}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Enable or disable PLL for selected lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct phy_configure_opts_dp *dp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 rd_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Used to determine, which bits to check for or enable in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * PHY_PMA_XCVR_PLLCLK_EN register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 pll_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Used to enable or disable lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 pll_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Select values of registers and mask, depending on enabled lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) switch (dp->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case (1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pll_bits = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* lanes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case (2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pll_bits = 0x00000003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* lanes 0-3, all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pll_bits = 0x0000000F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pll_val = pll_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pll_val = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Wait for acknowledgment from PHY. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = regmap_read_poll_timeout(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PHY_PMA_XCVR_PLLCLK_EN_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) rd_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) (rd_val & pll_bits) == pll_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0, POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ndelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * Perform register operations related to setting link rate, once powerstate is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * set and PLL disable request was processed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Disable the cmn_pll0_en before re-programming the new data rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Wait for PLL ready de-assertion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) read_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ((read_val >> 2) & 0x01) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0, POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ndelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* DP Rate Change - VCO Output settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* PMA common configuration 19.2MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dp->ssc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* PMA common configuration 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dp->ssc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Enable the cmn_pll0_en. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Wait for PLL ready assertion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) read_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (read_val & 0x01) != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 0, POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Verify, that parameters to configure PHY with are correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* If changing link rate was required, verify it's supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (dp->set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) switch (dp->link_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case 2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case 2430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case 3240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case 4320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* valid bit rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Verify lane count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) switch (dp->lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* valid lane count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Check against actual number of PHY's lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (dp->lanes > inst->num_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * If changing voltages is required, check swing and pre-emphasis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * levels, per-lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (dp->set_voltages) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Lane count verified previously. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) for (i = 0; i < dp->lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (dp->voltage[i] > 3 || dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Sum of voltage swing and pre-emphasis levels cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * exceed 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (dp->voltage[i] + dp->pre[i] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u32 num_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 pwr_state = cdns_torrent_dp_read(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PHY_PMA_XCVR_POWER_STATE_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 pll_clk_en = cdns_torrent_dp_read(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PHY_PMA_XCVR_PLLCLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Lane 0 is always enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PHY_POWER_STATE_LN_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pll_clk_en &= ~0x01U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (num_lanes > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* lane 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PHY_POWER_STATE_LN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pll_clk_en &= ~(0x01U << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (num_lanes > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* lanes 2 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PHY_POWER_STATE_LN_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PHY_POWER_STATE_LN_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pll_clk_en &= ~(0x01U << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pll_clk_en &= ~(0x01U << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Configure lane count as required. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u8 lane_mask = (1 << dp->lanes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) value = cdns_torrent_dp_read(regmap, PHY_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* clear pma_tx_elec_idle_ln_* bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) value &= ~PMA_TX_ELEC_IDLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PMA_TX_ELEC_IDLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cdns_torrent_dp_write(regmap, PHY_RESET, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* reset the link by asserting phy_l00_reset_n low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cdns_torrent_dp_write(regmap, PHY_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) value & (~PHY_L00_RESET_N_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * Assert lane reset on unused lanes and lane 0 so they remain in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * and powered down when re-enabling the link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) cdns_torrent_dp_write(regmap, PHY_RESET, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* release phy_l0*_reset_n based on used laneCount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) cdns_torrent_dp_write(regmap, PHY_RESET, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Wait, until PHY gets ready after releasing PHY reset signal. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ndelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) /* Configure link rate as required. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) POWERSTATE_A3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ndelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ndelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) POWERSTATE_A2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) POWERSTATE_A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ndelay(900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Configure voltage swing and pre-emphasis for all enabled lanes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct phy_configure_opts_dp *dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) for (lane = 0; lane < dp->lanes; lane++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) TX_DIAG_ACYA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * current state of the analog TX driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) val |= TX_DIAG_ACYA_HBDC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) TX_DIAG_ACYA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) TX_TXCC_CTRL, 0x08A4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) DRV_DIAG_TX_DRV, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) TX_TXCC_MGNFS_MULT_000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) TX_TXCC_CPOST_MULT_00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) TX_DIAG_ACYA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * analog TX driver to reflect the new programmed one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) val &= ~TX_DIAG_ACYA_HBDC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) TX_DIAG_ACYA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int cdns_torrent_dp_configure(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_err(&phy->dev, "invalid params for phy configure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (opts->dp.set_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (opts->dp.set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (opts->dp.set_voltages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int cdns_torrent_dp_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) unsigned char lane_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) switch (cdns_phy->ref_clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case REF_CLK_19_2MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case REF_CLK_25MHz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Valid Ref Clock Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* PHY PMA registers configuration function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) cdns_torrent_dp_pma_cfg(cdns_phy, inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * Set lines power state to A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * Set lines pll clk enable to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * used lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) lane_bits = (1 << inst->num_lanes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) cdns_torrent_dp_write(regmap, PHY_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* PHY PMA registers configuration functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* Initialize PHY with max supported link rate, without SSC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) cdns_phy->max_bit_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) cdns_phy->max_bit_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) inst->num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* take out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) cdns_torrent_phy_on(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) reg & 1, 0, POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(cdns_phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) "timeout waiting for PMA common ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct cdns_torrent_inst *inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* PMA common configuration 19.2MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* PMA common configuration 25MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* PMA lane configuration to deal with multi-link operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) for (i = 0; i < inst->num_lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct regmap *regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* refclock registers - assumes 19.2 MHz refclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* PLL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * Set registers responsible for enabling and configuring SSC, with second and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * third register values provided by parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) u32 ctrl2_val, u32 ctrl3_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct regmap *regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u32 rate, bool ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct regmap *regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Assumes 19.2 MHz refclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* Setting VCO for 10.8GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) CMN_PLL0_INTDIV_M0, 0x0119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) CMN_PLL0_FRACDIVL_M0, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) CMN_PLL0_HIGH_THR_M0, 0x00BC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) CMN_PLL1_INTDIV_M0, 0x0119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) CMN_PLL1_FRACDIVL_M0, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) CMN_PLL1_HIGH_THR_M0, 0x00BC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) 0x006A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Setting VCO for 9.72GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case 2430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) case 3240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) CMN_PLL0_INTDIV_M0, 0x01FA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) CMN_PLL0_FRACDIVL_M0, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) CMN_PLL0_HIGH_THR_M0, 0x0152);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) CMN_PLL1_INTDIV_M0, 0x01FA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) CMN_PLL1_FRACDIVL_M0, 0x4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) CMN_PLL1_HIGH_THR_M0, 0x0152);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) 0x0069);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Setting VCO for 8.64GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) case 2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case 4320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) CMN_PLL0_INTDIV_M0, 0x01C2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) CMN_PLL0_FRACDIVL_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) CMN_PLL0_HIGH_THR_M0, 0x012C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) CMN_PLL1_INTDIV_M0, 0x01C2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) CMN_PLL1_FRACDIVL_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) CMN_PLL1_HIGH_THR_M0, 0x012C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) 0x0069);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Setting VCO for 8.1GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) CMN_PLL0_INTDIV_M0, 0x01A5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) CMN_PLL0_FRACDIVL_M0, 0xE000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) CMN_PLL0_HIGH_THR_M0, 0x011A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) CMN_PLL1_INTDIV_M0, 0x01A5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) CMN_PLL1_FRACDIVL_M0, 0xE000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) CMN_PLL1_HIGH_THR_M0, 0x011A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) 0x006A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (ssc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Set reset register values to disable SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) CMN_PLL0_SS_CTRL1_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) CMN_PLL0_SS_CTRL2_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) CMN_PLL0_SS_CTRL3_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) CMN_PLL0_SS_CTRL4_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) CMN_PLL1_SS_CTRL1_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) CMN_PLL1_SS_CTRL2_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) CMN_PLL1_SS_CTRL3_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) CMN_PLL1_SS_CTRL4_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct regmap *regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* refclock registers - assumes 25 MHz refclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* PLL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * Set registers responsible for enabling and configuring SSC, with second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) * register value provided by a parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) u32 ctrl2_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct regmap *regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) u32 rate, bool ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct regmap *regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Assumes 25 MHz refclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Setting VCO for 10.8GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Setting VCO for 9.72GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) case 2430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) case 3240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* Setting VCO for 8.64GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) case 2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case 4320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) /* Setting VCO for 8.1GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (ssc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (ssc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) /* Set reset register values to disable SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) cdns_torrent_phy_write(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) u32 rate, u32 num_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) unsigned int clk_sel_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) unsigned int hsclk_div_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* 16'h0000 for single DP link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) clk_sel_val = 0x0f01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) hsclk_div_val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) case 2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 2430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) clk_sel_val = 0x0701;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) hsclk_div_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) case 3240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) clk_sel_val = 0x0b00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) hsclk_div_val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) case 4320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) clk_sel_val = 0x0301;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) hsclk_div_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) clk_sel_val = 0x0200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) hsclk_div_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* PMA lane configuration to deal with multi-link operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) for (i = 0; i < num_lanes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) unsigned int lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* Per lane, refclock-dependent receiver detection setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) TX_RCVDET_ST_TMR, 0x0780);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) TX_RCVDET_ST_TMR, 0x09C4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* Writing Tx/Rx Power State Controllers registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) TX_PSC_A0, 0x00FB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) TX_PSC_A2, 0x04AA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) TX_PSC_A3, 0x04AA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) RX_PSC_A0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) RX_PSC_A2, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) RX_PSC_A3, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) RX_PSC_CAL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) RX_REE_GCSM1_CTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) RX_REE_GCSM2_CTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) RX_REE_PERGCSM_CTRL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) XCVR_DIAG_BIDI_CTRL, 0x000F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) XCVR_DIAG_PLLDRC_CTRL, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) XCVR_DIAG_HSCLK_SEL, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) u32 num_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) enum phy_powerstate powerstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* Register value for power state for a single byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) u32 value_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) u32 read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) switch (powerstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) case (POWERSTATE_A0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) value_part = 0x01U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) case (POWERSTATE_A2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) value_part = 0x04U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* Powerstate A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) value_part = 0x08U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* Select values of registers and mask, depending on enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) * lane count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) switch (num_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* lane 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) case (1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) value = value_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) mask = 0x0000003FU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* lanes 0-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) case (2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) value = (value_part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) | (value_part << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) mask = 0x00003F3FU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* lanes 0-3, all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) value = (value_part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) | (value_part << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) | (value_part << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) | (value_part << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) mask = 0x3F3F3F3FU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* Set power state A<n>. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* Wait, until PHY acknowledges power state completion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) read_val, (read_val & mask) == value, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ndelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) unsigned int read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) * master lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) read_val, read_val & 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) 0, POLL_TIMEOUT_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) dev_err(cdns_phy->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) "timeout waiting for link PLL clock enable ack\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ndelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) POWERSTATE_A2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) POWERSTATE_A0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static int cdns_torrent_phy_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) u32 read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (cdns_phy->nsubnodes == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* Take the PHY lane group out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) reset_control_deassert(inst->lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* Take the PHY out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ret = reset_control_deassert(cdns_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) * Wait for cmn_ready assertion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) * PHY_PMA_CMN_CTRL1[0] == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) read_val, read_val, 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) PLL_LOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static int cdns_torrent_phy_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (cdns_phy->nsubnodes != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret = reset_control_assert(cdns_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return reset_control_assert(inst->lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) u32 block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) u8 reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) const struct regmap_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct cdns_regmap_cdb_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ctx->base = base + block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ctx->reg_offset_shift = reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return devm_regmap_init(dev, NULL, ctx, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct device *dev = cdns_phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct regmap_field *field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) regmap = cdns_phy->regmap_dptx_phy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) dev_err(dev, "PHY_RESET reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) cdns_phy->phy_reset_ctrl = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct device *dev = cdns_phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct regmap_field *field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) regmap = cdns_phy->regmap_phy_pcs_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) cdns_phy->phy_pll_cfg = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) regmap = cdns_phy->regmap_phy_pma_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) cdns_phy->phy_pma_cmn_ctrl_1 = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) regmap = cdns_phy->regmap_phy_pma_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) cdns_phy->phy_pma_cmn_ctrl_2 = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) regmap = cdns_phy->regmap_phy_pma_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) cdns_phy->phy_pma_pll_raw_ctrl = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) void __iomem *base = cdns_phy->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct device *dev = cdns_phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) u8 reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) u32 block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) block_offset = TORRENT_DPTX_PHY_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) regmap = cdns_regmap_init(dev, base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) &cdns_torrent_dptx_phy_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) dev_err(dev, "Failed to init DPTX PHY regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) cdns_phy->regmap_dptx_phy_reg = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) void __iomem *sd_base = cdns_phy->sd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) u8 block_offset_shift, reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) struct device *dev = cdns_phy->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) u32 block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) block_offset_shift = cdns_phy->init_data->block_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) for (i = 0; i < MAX_NUM_LANES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) reg_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) regmap = cdns_regmap_init(dev, sd_base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) &cdns_torrent_tx_lane_cdb_config[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) dev_err(dev, "Failed to init tx lane CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) cdns_phy->regmap_tx_lane_cdb[i] = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) reg_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) regmap = cdns_regmap_init(dev, sd_base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) &cdns_torrent_rx_lane_cdb_config[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) dev_err(dev, "Failed to init rx lane CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) cdns_phy->regmap_rx_lane_cdb[i] = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) block_offset = TORRENT_COMMON_CDB_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) regmap = cdns_regmap_init(dev, sd_base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) &cdns_torrent_common_cdb_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) dev_err(dev, "Failed to init common CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) cdns_phy->regmap_common_cdb = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) regmap = cdns_regmap_init(dev, sd_base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) &cdns_torrent_phy_pcs_cmn_cdb_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) cdns_phy->regmap_phy_pcs_common_cdb = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) regmap = cdns_regmap_init(dev, sd_base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) &cdns_torrent_phy_pma_cmn_cdb_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) cdns_phy->regmap_phy_pma_common_cdb = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static int cdns_torrent_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) const struct cdns_torrent_data *init_data = cdns_phy->init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) enum cdns_torrent_phy_type phy_type = inst->phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) struct cdns_torrent_vals *pcs_cmn_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) struct cdns_reg_pairs *reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) u32 num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (cdns_phy->nsubnodes > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (phy_type == TYPE_DP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return cdns_torrent_dp_init(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * Spread spectrum generation is not required or supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) * for SGMII/QSGMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ssc = NO_SSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* PHY configuration specific registers for single link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (link_cmn_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) reg_pairs = link_cmn_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) num_regs = link_cmn_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * First array value in link_cmn_vals must be of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * PHY_PLL_CFG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) for (i = 1; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) regmap_write(regmap, reg_pairs[i].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) reg_pairs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (xcvr_diag_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) reg_pairs = xcvr_diag_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) num_regs = xcvr_diag_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) for (i = 0; i < inst->num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) for (j = 0; j < num_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) regmap_write(regmap, reg_pairs[j].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) reg_pairs[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* PHY PCS common registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (pcs_cmn_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) reg_pairs = pcs_cmn_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) num_regs = pcs_cmn_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) regmap = cdns_phy->regmap_phy_pcs_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) for (i = 0; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) regmap_write(regmap, reg_pairs[i].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) reg_pairs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* PMA common registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (cmn_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) reg_pairs = cmn_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) num_regs = cmn_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) for (i = 0; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) regmap_write(regmap, reg_pairs[i].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) reg_pairs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /* PMA TX lane registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (tx_ln_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) reg_pairs = tx_ln_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) num_regs = tx_ln_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) for (i = 0; i < inst->num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) for (j = 0; j < num_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) regmap_write(regmap, reg_pairs[j].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) reg_pairs[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* PMA RX lane registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (rx_ln_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) reg_pairs = rx_ln_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) num_regs = rx_ln_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) for (i = 0; i < inst->num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) for (j = 0; j < num_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) regmap_write(regmap, reg_pairs[j].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) reg_pairs[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) const struct cdns_torrent_data *init_data = cdns_phy->init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct cdns_torrent_vals *pcs_cmn_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) int i, j, node, mlane, num_lanes, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct cdns_reg_pairs *reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) enum cdns_torrent_ssc_mode ssc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) u32 num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* Maximum 2 links (subnodes) are supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (cdns_phy->nsubnodes != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) phy_t1 = cdns_phy->phys[0].phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) phy_t2 = cdns_phy->phys[1].phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * First configure the PHY for first link with phy_t1. Get the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * values as [phy_t1][phy_t2][ssc].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) for (node = 0; node < cdns_phy->nsubnodes; node++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (node == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * If first link with phy_t1 is configured, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * configure the PHY for second link with phy_t2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * Get the array values as [phy_t2][phy_t1][ssc].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) tmp_phy_type = phy_t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) phy_t1 = phy_t2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) phy_t2 = tmp_phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) mlane = cdns_phy->phys[node].mlane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ssc = cdns_phy->phys[node].ssc_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) num_lanes = cdns_phy->phys[node].num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) * PHY configuration specific registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) * link_cmn_vals depend on combination of PHY types being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) * configured and are common for both PHY types, so array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) * values should be same for [phy_t1][phy_t2][ssc] and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) * [phy_t2][phy_t1][ssc].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) * xcvr_diag_vals also depend on combination of PHY types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) * being configured, but these can be different for particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * PHY type and are per lane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (link_cmn_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) reg_pairs = link_cmn_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) num_regs = link_cmn_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * First array value in link_cmn_vals must be of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) * PHY_PLL_CFG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) regmap_field_write(cdns_phy->phy_pll_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) reg_pairs[0].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) for (i = 1; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) regmap_write(regmap, reg_pairs[i].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) reg_pairs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (xcvr_diag_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) reg_pairs = xcvr_diag_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) num_regs = xcvr_diag_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) for (i = 0; i < num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) for (j = 0; j < num_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) regmap_write(regmap, reg_pairs[j].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) reg_pairs[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* PHY PCS common registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (pcs_cmn_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) reg_pairs = pcs_cmn_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) num_regs = pcs_cmn_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) regmap = cdns_phy->regmap_phy_pcs_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) for (i = 0; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) regmap_write(regmap, reg_pairs[i].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) reg_pairs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* PMA common registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (cmn_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) reg_pairs = cmn_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) num_regs = cmn_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) regmap = cdns_phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) for (i = 0; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) regmap_write(regmap, reg_pairs[i].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) reg_pairs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* PMA TX lane registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (tx_ln_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) reg_pairs = tx_ln_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) num_regs = tx_ln_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) for (i = 0; i < num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) for (j = 0; j < num_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) regmap_write(regmap, reg_pairs[j].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) reg_pairs[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) /* PMA RX lane registers configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (rx_ln_vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) reg_pairs = rx_ln_vals->reg_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) num_regs = rx_ln_vals->num_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) for (i = 0; i < num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) for (j = 0; j < num_regs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) regmap_write(regmap, reg_pairs[j].off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) reg_pairs[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) reset_control_deassert(cdns_phy->phys[node].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* Take the PHY out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ret = reset_control_deassert(cdns_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static int cdns_torrent_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) struct cdns_torrent_phy *cdns_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) const struct cdns_torrent_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) int ret, subnodes, node = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) u32 total_num_lanes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) u8 init_dp_regmap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) u32 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* Get init data for this PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (!cdns_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) dev_set_drvdata(dev, cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) cdns_phy->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) cdns_phy->init_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (IS_ERR(cdns_phy->phy_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) dev_err(dev, "%s: failed to get reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) dev->of_node->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) return PTR_ERR(cdns_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) cdns_phy->apb_rst = devm_reset_control_get_optional(dev, "torrent_apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (IS_ERR(cdns_phy->apb_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) dev_err(dev, "%s: failed to get apb reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) dev->of_node->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) return PTR_ERR(cdns_phy->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) cdns_phy->clk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (IS_ERR(cdns_phy->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) dev_err(dev, "phy ref clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return PTR_ERR(cdns_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (IS_ERR(cdns_phy->sd_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) return PTR_ERR(cdns_phy->sd_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) subnodes = of_get_available_child_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (subnodes == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) dev_err(dev, "No available link subnodes found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ret = cdns_torrent_regmap_init(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ret = cdns_torrent_regfield_init(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) ret = clk_prepare_enable(cdns_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (!(cdns_phy->ref_clk_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) clk_disable_unprepare(cdns_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /* Enable APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) reset_control_deassert(cdns_phy->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) for_each_available_child_of_node(dev->of_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) struct phy *gphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* PHY subnode name must be 'phy'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (!(of_node_name_eq(child, "phy")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) cdns_phy->phys[node].lnk_rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) of_reset_control_array_get_exclusive(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dev_err(dev, "%s: failed to get reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) child->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) goto put_lnk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (of_property_read_u32(child, "reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) &cdns_phy->phys[node].mlane)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) dev_err(dev, "%s: No \"reg\"-property.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) child->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) child->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) switch (phy_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) case PHY_TYPE_PCIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) cdns_phy->phys[node].phy_type = TYPE_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) case PHY_TYPE_DP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) cdns_phy->phys[node].phy_type = TYPE_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) case PHY_TYPE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) cdns_phy->phys[node].phy_type = TYPE_SGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) case PHY_TYPE_QSGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) cdns_phy->phys[node].phy_type = TYPE_QSGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) case PHY_TYPE_USB3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) cdns_phy->phys[node].phy_type = TYPE_USB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) dev_err(dev, "Unsupported protocol\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (of_property_read_u32(child, "cdns,num-lanes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) &cdns_phy->phys[node].num_lanes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) child->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) total_num_lanes += cdns_phy->phys[node].num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /* Get SSC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) cdns_phy->phys[node].ssc_mode = NO_SSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) of_property_read_u32(child, "cdns,ssc-mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) &cdns_phy->phys[node].ssc_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (IS_ERR(gphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ret = PTR_ERR(gphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (cdns_phy->phys[node].phy_type == TYPE_DP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) switch (cdns_phy->phys[node].num_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* valid number of lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) dev_err(dev, "unsupported number of lanes: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) cdns_phy->phys[node].num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) of_property_read_u32(child, "cdns,max-bit-rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) &cdns_phy->max_bit_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) switch (cdns_phy->max_bit_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) case 1620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) case 2160:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) case 2430:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) case 2700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) case 3240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) case 4320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) case 5400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) case 8100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /* valid bit rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) dev_err(dev, "unsupported max bit rate: %dMbps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) cdns_phy->max_bit_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /* DPTX registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (IS_ERR(cdns_phy->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ret = PTR_ERR(cdns_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if (!init_dp_regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ret = cdns_torrent_dp_regmap_init(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) ret = cdns_torrent_dp_regfield_init(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) init_dp_regmap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) cdns_phy->phys[node].num_lanes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) cdns_phy->max_bit_rate / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) cdns_phy->max_bit_rate % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) gphy->attrs.mode = PHY_MODE_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) cdns_phy->phys[node].phy = gphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) phy_set_drvdata(gphy, &cdns_phy->phys[node]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) node++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) cdns_phy->nsubnodes = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (total_num_lanes > MAX_NUM_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dev_err(dev, "Invalid lane configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) goto put_lnk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (cdns_phy->nsubnodes > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) ret = cdns_torrent_phy_configure_multilink(cdns_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) goto put_lnk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) ret = PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) goto put_lnk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) node++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) put_lnk_rst:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) for (i = 0; i < node; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) reset_control_put(cdns_phy->phys[i].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) reset_control_assert(cdns_phy->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) clk_disable_unprepare(cdns_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static int cdns_torrent_phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) reset_control_assert(cdns_phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) reset_control_assert(cdns_phy->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) for (i = 0; i < cdns_phy->nsubnodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) reset_control_assert(cdns_phy->phys[i].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) reset_control_put(cdns_phy->phys[i].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) clk_disable_unprepare(cdns_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* USB and SGMII/QSGMII link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) {0x0002, PHY_PLL_CFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) {0x0000, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) {0x0001, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) {0x0041, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) {0x0011, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) {0x0003, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) {0x009B, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .reg_pairs = usb_sgmii_link_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) /* PCIe and USB Unique SSC link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) {0x0003, PHY_PLL_CFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) {0x0000, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) {0x0001, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) {0x0012, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) {0x0011, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) {0x0001, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .reg_pairs = pcie_usb_link_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* USB 100 MHz Ref clk, internal SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {0x0004, CMN_PLL0_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) {0x0004, CMN_PLL0_DSM_DIAG_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) {0x0004, CMN_PLL1_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {0x0064, CMN_PLL0_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) {0x0050, CMN_PLL0_INTDIV_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) {0x0064, CMN_PLL1_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) {0x0002, CMN_PLL0_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) {0x0002, CMN_PLL0_FRACDIVH_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) {0x0002, CMN_PLL1_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {0x0044, CMN_PLL0_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) {0x0036, CMN_PLL0_HIGH_THR_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {0x0044, CMN_PLL1_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) {0x0001, CMN_PLL0_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) {0x0001, CMN_PLL0_SS_CTRL1_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) {0x0001, CMN_PLL1_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) {0x011B, CMN_PLL0_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) {0x011B, CMN_PLL0_SS_CTRL2_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {0x011B, CMN_PLL1_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) {0x006E, CMN_PLL0_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {0x0058, CMN_PLL0_SS_CTRL3_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) {0x006E, CMN_PLL1_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) {0x000E, CMN_PLL0_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) {0x0012, CMN_PLL0_SS_CTRL4_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) {0x000E, CMN_PLL1_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .reg_pairs = usb_100_int_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) /* Single USB link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {0x0000, PHY_PLL_CFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {0x0000, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) {0x0001, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) {0x0041, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .reg_pairs = sl_usb_link_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .reg_pairs = sl_usb_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) /* USB PHY PCS common configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .reg_pairs = usb_phy_pcs_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) /* USB 100 MHz Ref clk, no SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) {0x02FF, TX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) {0x06AF, TX_PSC_A1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) {0x06AE, TX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) {0x06AE, TX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) {0x2A82, TX_TXCC_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) {0x0014, TX_TXCC_CPOST_MULT_01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) {0x0003, XCVR_DIAG_PSC_OVRD}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) {0x0D1D, RX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) {0x0D1D, RX_PSC_A1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) {0x0D00, RX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) {0x0500, RX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) {0x0013, RX_SIGDET_HL_FILT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) {0x0000, RX_REE_GCSM1_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) {0x0C02, RX_REE_ATTEN_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) {0x0330, RX_REE_SMGM_CTRL1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) {0x0300, RX_REE_SMGM_CTRL2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) {0x0019, RX_REE_TAP1_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) {0x0019, RX_REE_TAP2TON_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) {0x1004, RX_DIAG_SIGDET_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) {0x00F9, RX_DIAG_NQST_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) {0x0000, RX_DIAG_PI_CAP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) {0x0031, RX_DIAG_PI_RATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) {0x0001, RX_DIAG_ACYA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) {0x018C, RX_CDRLF_CNFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) {0x0003, RX_CDRLF_CNFG3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .reg_pairs = usb_100_no_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .reg_pairs = usb_100_no_ssc_tx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .reg_pairs = usb_100_no_ssc_rx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* Single link USB, 100 MHz Ref clk, internal SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) {0x0004, CMN_PLL0_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) {0x0004, CMN_PLL1_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) {0x0064, CMN_PLL0_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) {0x0064, CMN_PLL1_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {0x0002, CMN_PLL0_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) {0x0002, CMN_PLL1_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) {0x0044, CMN_PLL0_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) {0x0044, CMN_PLL1_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) {0x0001, CMN_PLL0_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) {0x0001, CMN_PLL1_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) {0x011B, CMN_PLL0_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) {0x011B, CMN_PLL1_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) {0x006E, CMN_PLL0_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) {0x006E, CMN_PLL1_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) {0x000E, CMN_PLL0_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) {0x000E, CMN_PLL1_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /* PCIe and SGMII/QSGMII Unique SSC link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) {0x0003, PHY_PLL_CFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) {0x0000, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) {0x0001, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) {0x0012, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) {0x0011, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) {0x0003, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) {0x009B, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .reg_pairs = pcie_sgmii_link_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /* SGMII 100 MHz Ref clk, no SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) {0x3700, CMN_DIAG_BIAS_OVRD1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) {0x0008, CMN_TXPUCAL_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) {0x0008, CMN_TXPDCAL_TUNE}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) {0x00F3, TX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) {0x04A2, TX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) {0x04A2, TX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) {0x0000, TX_TXCC_CPOST_MULT_00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) {0x00B3, DRV_DIAG_TX_DRV}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) {0x091D, RX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) {0x0900, RX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) {0x0100, RX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) {0x03C7, RX_REE_GCSM1_EQENM_PH1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) {0x01C7, RX_REE_GCSM1_EQENM_PH2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) {0x0000, RX_DIAG_DFE_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) {0x0019, RX_REE_TAP1_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) {0x0019, RX_REE_TAP2TON_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) {0x0098, RX_DIAG_NQST_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) {0x0000, RX_DIAG_PI_CAP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) {0x0010, RX_DIAG_PI_RATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) {0x0001, RX_DIAG_ACYA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) {0x018C, RX_CDRLF_CNFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .reg_pairs = sgmii_100_no_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /* SGMII 100 MHz Ref clk, internal SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) {0x0004, CMN_PLL0_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) {0x0004, CMN_PLL0_DSM_DIAG_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) {0x0004, CMN_PLL1_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) {0x0064, CMN_PLL0_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) {0x0050, CMN_PLL0_INTDIV_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) {0x0064, CMN_PLL1_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) {0x0002, CMN_PLL0_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) {0x0002, CMN_PLL0_FRACDIVH_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) {0x0002, CMN_PLL1_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) {0x0044, CMN_PLL0_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) {0x0036, CMN_PLL0_HIGH_THR_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) {0x0044, CMN_PLL1_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) {0x0001, CMN_PLL0_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) {0x0001, CMN_PLL0_SS_CTRL1_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {0x0001, CMN_PLL1_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) {0x011B, CMN_PLL0_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) {0x011B, CMN_PLL0_SS_CTRL2_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) {0x011B, CMN_PLL1_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) {0x006E, CMN_PLL0_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) {0x0058, CMN_PLL0_SS_CTRL3_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) {0x006E, CMN_PLL1_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) {0x000E, CMN_PLL0_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) {0x0012, CMN_PLL0_SS_CTRL4_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) {0x000E, CMN_PLL1_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) {0x3700, CMN_DIAG_BIAS_OVRD1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) {0x0008, CMN_TXPUCAL_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) {0x0008, CMN_TXPDCAL_TUNE}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .reg_pairs = sgmii_100_int_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* QSGMII 100 MHz Ref clk, no SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) {0x0003, CMN_PLL1_VCOCAL_TCTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) {0x00F3, TX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) {0x04A2, TX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) {0x04A2, TX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) {0x0000, TX_TXCC_CPOST_MULT_00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) {0x0003, DRV_DIAG_TX_DRV}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) {0x091D, RX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) {0x0900, RX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) {0x0100, RX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) {0x03C7, RX_REE_GCSM1_EQENM_PH1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) {0x01C7, RX_REE_GCSM1_EQENM_PH2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) {0x0000, RX_DIAG_DFE_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) {0x0019, RX_REE_TAP1_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) {0x0019, RX_REE_TAP2TON_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) {0x0098, RX_DIAG_NQST_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) {0x0000, RX_DIAG_PI_CAP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) {0x0010, RX_DIAG_PI_RATE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) {0x0001, RX_DIAG_ACYA},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) {0x018C, RX_CDRLF_CNFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) /* QSGMII 100 MHz Ref clk, internal SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) {0x0004, CMN_PLL0_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) {0x0004, CMN_PLL0_DSM_DIAG_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) {0x0004, CMN_PLL1_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) {0x0064, CMN_PLL0_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) {0x0050, CMN_PLL0_INTDIV_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) {0x0064, CMN_PLL1_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) {0x0002, CMN_PLL0_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) {0x0002, CMN_PLL0_FRACDIVH_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) {0x0002, CMN_PLL1_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) {0x0044, CMN_PLL0_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) {0x0036, CMN_PLL0_HIGH_THR_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) {0x0044, CMN_PLL1_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) {0x0001, CMN_PLL0_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) {0x0001, CMN_PLL0_SS_CTRL1_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) {0x0001, CMN_PLL1_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) {0x011B, CMN_PLL0_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) {0x011B, CMN_PLL0_SS_CTRL2_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) {0x011B, CMN_PLL1_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) {0x006E, CMN_PLL0_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) {0x0058, CMN_PLL0_SS_CTRL3_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) {0x006E, CMN_PLL1_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) {0x000E, CMN_PLL0_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) {0x0012, CMN_PLL0_SS_CTRL4_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) {0x000E, CMN_PLL1_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) /* Single SGMII/QSGMII link configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) {0x0000, PHY_PLL_CFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) {0x0000, XCVR_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) {0x0003, XCVR_DIAG_HSCLK_DIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) {0x0013, XCVR_DIAG_PLLDRC_CTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .reg_pairs = sl_sgmii_link_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) {0x0004, CMN_PLL0_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) {0x0004, CMN_PLL0_DSM_DIAG_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) {0x0004, CMN_PLL1_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) {0x0064, CMN_PLL0_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) {0x0050, CMN_PLL0_INTDIV_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) {0x0064, CMN_PLL1_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) {0x0002, CMN_PLL0_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) {0x0002, CMN_PLL0_FRACDIVH_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) {0x0002, CMN_PLL1_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) {0x0044, CMN_PLL0_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) {0x0036, CMN_PLL0_HIGH_THR_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) {0x0044, CMN_PLL1_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) {0x0001, CMN_PLL0_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) {0x0001, CMN_PLL0_SS_CTRL1_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) {0x0001, CMN_PLL1_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) {0x011B, CMN_PLL0_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) {0x011B, CMN_PLL0_SS_CTRL2_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) {0x011B, CMN_PLL1_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) {0x006E, CMN_PLL0_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) {0x0058, CMN_PLL0_SS_CTRL3_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) {0x006E, CMN_PLL1_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) {0x000E, CMN_PLL0_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) {0x0012, CMN_PLL0_SS_CTRL4_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) {0x000E, CMN_PLL1_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .reg_pairs = pcie_100_int_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) /* Single link PCIe, 100 MHz Ref clk, internal SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) {0x0004, CMN_PLL0_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) {0x0004, CMN_PLL0_DSM_DIAG_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) {0x0004, CMN_PLL1_DSM_DIAG_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) {0x0064, CMN_PLL0_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) {0x0050, CMN_PLL0_INTDIV_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) {0x0050, CMN_PLL1_INTDIV_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) {0x0002, CMN_PLL0_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) {0x0002, CMN_PLL0_FRACDIVH_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) {0x0002, CMN_PLL1_FRACDIVH_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) {0x0044, CMN_PLL0_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) {0x0036, CMN_PLL0_HIGH_THR_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) {0x0036, CMN_PLL1_HIGH_THR_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) {0x0001, CMN_PLL0_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) {0x0001, CMN_PLL0_SS_CTRL1_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) {0x0001, CMN_PLL1_SS_CTRL1_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) {0x011B, CMN_PLL0_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) {0x011B, CMN_PLL0_SS_CTRL2_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) {0x011B, CMN_PLL1_SS_CTRL2_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) {0x006E, CMN_PLL0_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) {0x0058, CMN_PLL0_SS_CTRL3_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) {0x0058, CMN_PLL1_SS_CTRL3_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) {0x000E, CMN_PLL0_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) {0x0012, CMN_PLL0_SS_CTRL4_M1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) {0x0012, CMN_PLL1_SS_CTRL4_M0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) {0x0003, CMN_PLL1_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) {0x0003, CMN_PLL0_VCOCAL_TCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) {0x0003, CMN_PLL1_VCOCAL_TCTRL}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) {0x0019, RX_REE_TAP1_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) {0x0019, RX_REE_TAP2TON_CLIP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) {0x0001, RX_DIAG_ACYA}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) static const struct cdns_torrent_data cdns_map_torrent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .block_offset_shift = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .reg_offset_shift = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) [NO_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) [NO_SSC] = &sl_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) [NO_SSC] = &sl_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) [NO_SSC] = &sl_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) [NO_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) .xcvr_diag_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) .pcs_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) .cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) .tx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) .rx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) static const struct cdns_torrent_data ti_j721e_map_torrent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) .block_offset_shift = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) .reg_offset_shift = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) .link_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) [NO_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) [NO_SSC] = &sl_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) [NO_SSC] = &sl_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) [NO_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) [NO_SSC] = &sl_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) [NO_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) [NO_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) .xcvr_diag_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) .pcs_cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) [NO_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) .cmn_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) [NO_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) .tx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) [NO_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) [EXTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) [INTERNAL_SSC] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) .rx_ln_vals = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) [TYPE_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) [TYPE_NONE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) [TYPE_PCIE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) [TYPE_SGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) [TYPE_QSGMII] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) static const struct of_device_id cdns_torrent_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) .compatible = "cdns,torrent-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) .data = &cdns_map_torrent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) .compatible = "ti,j721e-serdes-10g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) .data = &ti_j721e_map_torrent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) static struct platform_driver cdns_torrent_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) .probe = cdns_torrent_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) .remove = cdns_torrent_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) .name = "cdns-torrent-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) .of_match_table = cdns_torrent_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) module_platform_driver(cdns_torrent_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) MODULE_AUTHOR("Cadence Design Systems, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) MODULE_DESCRIPTION("Cadence Torrent PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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