^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cadence Sierra PHY Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Cadence Design Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Alan Douglas <adouglas@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PHY register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIERRA_COMMON_CDB_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SIERRA_MACRO_ID_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SIERRA_CMN_PLLLC_MODE_PREG 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ((0x4000 << (block_offset)) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (((ln) << 9) << (reg_offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SIERRA_DET_STANDEC_A_PREG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SIERRA_DET_STANDEC_B_PREG 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SIERRA_DET_STANDEC_C_PREG 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SIERRA_DET_STANDEC_D_PREG 0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SIERRA_DET_STANDEC_E_PREG 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SIERRA_PSM_A0IN_TMR_PREG 0x009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SIERRA_PSM_DIAG_PREG 0x015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SIERRA_PSC_TX_A0_PREG 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SIERRA_PSC_TX_A1_PREG 0x029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SIERRA_PSC_TX_A2_PREG 0x02A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SIERRA_PSC_TX_A3_PREG 0x02B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIERRA_PSC_RX_A0_PREG 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SIERRA_PSC_RX_A1_PREG 0x031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SIERRA_PSC_RX_A2_PREG 0x032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIERRA_PSC_RX_A3_PREG 0x033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIERRA_PLLCTRL_STATUS_PREG 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SIERRA_DFE_BIASTRIM_PREG 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SIERRA_CLKPATHCTRL_TMR_PREG 0x081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SIERRA_CREQ_EQ_CTRL_PREG 0x093
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SIERRA_CREQ_SPARE_PREG 0x096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SIERRA_CTLELUT_CTRL_PREG 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SIERRA_DEQ_PHALIGN_CTRL 0x0C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SIERRA_DEQ_GLUT0 0x0E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SIERRA_DEQ_GLUT1 0x0E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SIERRA_DEQ_GLUT2 0x0EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SIERRA_DEQ_GLUT3 0x0EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SIERRA_DEQ_GLUT4 0x0EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SIERRA_DEQ_GLUT5 0x0ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SIERRA_DEQ_GLUT6 0x0EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SIERRA_DEQ_GLUT7 0x0EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SIERRA_DEQ_GLUT8 0x0F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SIERRA_DEQ_GLUT9 0x0F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SIERRA_DEQ_GLUT10 0x0F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SIERRA_DEQ_GLUT11 0x0F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SIERRA_DEQ_GLUT12 0x0F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SIERRA_DEQ_GLUT13 0x0F5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SIERRA_DEQ_GLUT14 0x0F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SIERRA_DEQ_GLUT15 0x0F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SIERRA_DEQ_GLUT16 0x0F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SIERRA_DEQ_ALUT0 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SIERRA_DEQ_ALUT1 0x109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SIERRA_DEQ_ALUT2 0x10A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SIERRA_DEQ_ALUT3 0x10B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SIERRA_DEQ_ALUT4 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SIERRA_DEQ_ALUT5 0x10D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SIERRA_DEQ_ALUT6 0x10E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SIERRA_DEQ_ALUT7 0x10F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SIERRA_DEQ_ALUT8 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SIERRA_DEQ_ALUT9 0x111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SIERRA_DEQ_ALUT10 0x112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SIERRA_DEQ_ALUT11 0x113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SIERRA_DEQ_ALUT12 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SIERRA_DEQ_ALUT13 0x115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SIERRA_DEQ_PICTRL_PREG 0x161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SIERRA_LFPSDET_SUPPORT_PREG 0x188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SIERRA_LFPSFILT_NS_PREG 0x18A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SIERRA_LFPSFILT_RD_PREG 0x18B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SIERRA_LFPSFILT_MP_PREG 0x18C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SIERRA_SIGDET_SUPPORT_PREG 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SIERRA_SDFILT_H2L_A_PREG 0x191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SIERRA_SDFILT_L2H_PREG 0x193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (0xc000 << (block_offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SIERRA_PHY_PLL_CFG 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SIERRA_MACRO_ID 0x00007364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SIERRA_MAX_LANES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PLL_LOCK_TIME 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct reg_field macro_id_type =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct reg_field phy_pll_cfg_1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct reg_field pllctrl_lock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct cdns_sierra_inst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 phy_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 mlane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct reset_control *lnk_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct cdns_reg_pairs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct cdns_sierra_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 id_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 block_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 pcie_cmn_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 pcie_ln_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 usb_cmn_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 usb_ln_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const struct cdns_reg_pairs *pcie_cmn_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const struct cdns_reg_pairs *pcie_ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct cdns_reg_pairs *usb_cmn_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct cdns_reg_pairs *usb_ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct cdns_regmap_cdb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct cdns_sierra_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct cdns_sierra_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct reset_control *phy_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct reset_control *apb_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct regmap *regmap_phy_config_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct regmap *regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct regmap_field *macro_id_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct regmap_field *phy_pll_cfg_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct clk *cmn_refclk_dig_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk *cmn_refclk1_dig_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int nsubnodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool autoconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct cdns_regmap_cdb_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 offset = reg << ctx->reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) writew(val, ctx->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct cdns_regmap_cdb_context *ctx = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 offset = reg << ctx->reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *val = readw(ctx->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define SIERRA_LANE_CDB_REGMAP_CONF(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "sierra_lane" n "_cdb", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .reg_stride = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .fast_io = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .reg_write = cdns_regmap_write, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .reg_read = cdns_regmap_read, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct regmap_config cdns_sierra_lane_cdb_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SIERRA_LANE_CDB_REGMAP_CONF("0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SIERRA_LANE_CDB_REGMAP_CONF("1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SIERRA_LANE_CDB_REGMAP_CONF("2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SIERRA_LANE_CDB_REGMAP_CONF("3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SIERRA_LANE_CDB_REGMAP_CONF("4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SIERRA_LANE_CDB_REGMAP_CONF("5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SIERRA_LANE_CDB_REGMAP_CONF("6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SIERRA_LANE_CDB_REGMAP_CONF("7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SIERRA_LANE_CDB_REGMAP_CONF("8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SIERRA_LANE_CDB_REGMAP_CONF("9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SIERRA_LANE_CDB_REGMAP_CONF("10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SIERRA_LANE_CDB_REGMAP_CONF("11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SIERRA_LANE_CDB_REGMAP_CONF("12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SIERRA_LANE_CDB_REGMAP_CONF("13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SIERRA_LANE_CDB_REGMAP_CONF("14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SIERRA_LANE_CDB_REGMAP_CONF("15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct regmap_config cdns_sierra_common_cdb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "sierra_common_cdb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .reg_write = cdns_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .reg_read = cdns_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct regmap_config cdns_sierra_phy_config_ctrl_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .name = "sierra_phy_config_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reg_write = cdns_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .reg_read = cdns_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int cdns_sierra_phy_init(struct phy *gphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const struct cdns_reg_pairs *cmn_vals, *ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 num_cmn_regs, num_ln_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Initialise the PHY registers, unless auto configured */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (phy->autoconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_set_rate(phy->cmn_refclk_dig_div, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_set_rate(phy->cmn_refclk1_dig_div, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ins->phy_type == PHY_TYPE_PCIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) num_cmn_regs = phy->init_data->pcie_cmn_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) num_ln_regs = phy->init_data->pcie_ln_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cmn_vals = phy->init_data->pcie_cmn_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ln_vals = phy->init_data->pcie_ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else if (ins->phy_type == PHY_TYPE_USB3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) num_cmn_regs = phy->init_data->usb_cmn_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) num_ln_regs = phy->init_data->usb_ln_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cmn_vals = phy->init_data->usb_cmn_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ln_vals = phy->init_data->usb_ln_vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regmap = phy->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (j = 0; j < num_cmn_regs ; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < ins->num_lanes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for (j = 0; j < num_ln_regs ; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regmap = phy->regmap_lane_cdb[i + ins->mlane];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int cdns_sierra_phy_on(struct phy *gphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = reset_control_deassert(sp->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(dev, "Failed to take the PHY out of reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Take the PHY lane group out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = reset_control_deassert(ins->lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(dev, "Failed to take the PHY lane out of reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val, val, 1000, PLL_LOCK_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(dev, "PLL lock of lane failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int cdns_sierra_phy_off(struct phy *gphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return reset_control_assert(ins->lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int cdns_sierra_phy_reset(struct phy *gphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reset_control_assert(sp->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reset_control_deassert(sp->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct phy_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .init = cdns_sierra_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .power_on = cdns_sierra_phy_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .power_off = cdns_sierra_phy_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .reset = cdns_sierra_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct device_node *child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (of_property_read_u32(child, "reg", &inst->mlane))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (of_property_read_u32(child, "cdns,phy-type", &inst->phy_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct of_device_id cdns_sierra_id_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 block_offset, u8 reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) const struct regmap_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct cdns_regmap_cdb_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ctx->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ctx->base = base + block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ctx->reg_offset_shift = reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return devm_regmap_init(dev, NULL, ctx, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int cdns_regfield_init(struct cdns_sierra_phy *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct regmap_field *field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regmap = sp->regmap_common_cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) sp->macro_id_type = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) regmap = sp->regmap_phy_config_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) sp->phy_pll_cfg_1 = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) for (i = 0; i < SIERRA_MAX_LANES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) regmap = sp->regmap_lane_cdb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (IS_ERR(field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return PTR_ERR(field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) sp->pllctrl_lock[i] = field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) void __iomem *base, u8 block_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u8 reg_offset_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < SIERRA_MAX_LANES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) reg_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regmap = cdns_regmap_init(dev, base, block_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &cdns_sierra_lane_cdb_config[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_err(dev, "Failed to init lane CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) sp->regmap_lane_cdb[i] = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) &cdns_sierra_common_cdb_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(dev, "Failed to init common CDB regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sp->regmap_common_cdb = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &cdns_sierra_phy_config_ctrl_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_err(dev, "Failed to init PHY config and control regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sp->regmap_phy_config_ctrl = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int cdns_sierra_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct cdns_sierra_phy *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct cdns_sierra_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int id_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int i, ret, node = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct device_node *dn = dev->of_node, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (of_get_child_count(dn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Get init data for this PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) match = of_match_device(cdns_sierra_id_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) data = (struct cdns_sierra_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sp = devm_kzalloc(dev, sizeof(*sp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_set_drvdata(dev, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) sp->init_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev, "missing \"reg\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) data->reg_offset_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = cdns_regfield_init(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) platform_set_drvdata(pdev, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sp->clk = devm_clk_get_optional(dev, "phy_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (IS_ERR(sp->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(dev, "failed to get clock phy_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return PTR_ERR(sp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (IS_ERR(sp->phy_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(dev, "failed to get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return PTR_ERR(sp->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (IS_ERR(sp->apb_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_err(dev, "failed to get apb reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return PTR_ERR(sp->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dev_err(dev, "cmn_refclk_dig_div clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sp->cmn_refclk_dig_div = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) sp->cmn_refclk1_dig_div = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = clk_prepare_enable(sp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Enable APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reset_control_deassert(sp->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Check that PHY is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regmap_field_read(sp->macro_id_type, &id_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (sp->init_data->id_value != id_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) for_each_available_child_of_node(dn, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct phy *gphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) sp->phys[node].lnk_rst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) of_reset_control_array_get_exclusive(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(sp->phys[node].lnk_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(dev, "failed to get reset %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) child->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = PTR_ERR(sp->phys[node].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto put_child2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!sp->autoconf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = cdns_sierra_get_optional(&sp->phys[node], child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_err(dev, "missing property in node %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) child->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) sp->num_lanes += sp->phys[node].num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) gphy = devm_phy_create(dev, child, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (IS_ERR(gphy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = PTR_ERR(gphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sp->phys[node].phy = gphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) phy_set_drvdata(gphy, &sp->phys[node]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) node++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sp->nsubnodes = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (sp->num_lanes > SIERRA_MAX_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_err(dev, "Invalid lane configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto put_child2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* If more than one subnode, configure the PHY as multilink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!sp->autoconf && sp->nsubnodes > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) regmap_field_write(sp->phy_pll_cfg_1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) node++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) put_child2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; i < node; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) reset_control_put(sp->phys[i].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_disable_unprepare(sp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) reset_control_assert(sp->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int cdns_sierra_phy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) reset_control_assert(phy->phy_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) reset_control_assert(phy->apb_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * The device level resets will be put automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Need to put the subnode resets here though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) for (i = 0; i < phy->nsubnodes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) reset_control_assert(phy->phys[i].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) reset_control_put(phy->phys[i].lnk_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* refclk100MHz_32b_PCIe_ln_ext_ssc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* refclk100MHz_20b_USB_ln_ext_ssc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x000F, SIERRA_DET_STANDEC_B_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x55A5, SIERRA_DET_STANDEC_C_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x69ad, SIERRA_DET_STANDEC_D_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x0241, SIERRA_DET_STANDEC_E_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0xCF00, SIERRA_PSM_DIAG_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x001F, SIERRA_PSC_TX_A0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x0007, SIERRA_PSC_TX_A1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x0003, SIERRA_PSC_TX_A2_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x0003, SIERRA_PSC_TX_A3_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x0FFF, SIERRA_PSC_RX_A0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x0003, SIERRA_PSC_RX_A1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x0003, SIERRA_PSC_RX_A2_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x0001, SIERRA_PSC_RX_A3_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x2512, SIERRA_DFE_BIASTRIM_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x0000, SIERRA_CREQ_SPARE_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x8452, SIERRA_CTLELUT_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x0014, SIERRA_DEQ_GLUT0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x0014, SIERRA_DEQ_GLUT1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x0014, SIERRA_DEQ_GLUT2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x0014, SIERRA_DEQ_GLUT3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x0014, SIERRA_DEQ_GLUT4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x0014, SIERRA_DEQ_GLUT5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x0014, SIERRA_DEQ_GLUT6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x0014, SIERRA_DEQ_GLUT7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x0014, SIERRA_DEQ_GLUT8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x0014, SIERRA_DEQ_GLUT9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x0014, SIERRA_DEQ_GLUT10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x0014, SIERRA_DEQ_GLUT11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x0014, SIERRA_DEQ_GLUT12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x0014, SIERRA_DEQ_GLUT13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x0014, SIERRA_DEQ_GLUT14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x0014, SIERRA_DEQ_GLUT15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x0014, SIERRA_DEQ_GLUT16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x0BAE, SIERRA_DEQ_ALUT0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x0AEB, SIERRA_DEQ_ALUT1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x0A28, SIERRA_DEQ_ALUT2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x0965, SIERRA_DEQ_ALUT3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x08A2, SIERRA_DEQ_ALUT4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x07DF, SIERRA_DEQ_ALUT5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x071C, SIERRA_DEQ_ALUT6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x0659, SIERRA_DEQ_ALUT7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x0596, SIERRA_DEQ_ALUT8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x0514, SIERRA_DEQ_ALUT9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x0492, SIERRA_DEQ_ALUT10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x0410, SIERRA_DEQ_ALUT11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x038E, SIERRA_DEQ_ALUT12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x030C, SIERRA_DEQ_ALUT13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x0033, SIERRA_DEQ_PICTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x000F, SIERRA_LFPSFILT_NS_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x0009, SIERRA_LFPSFILT_RD_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x0001, SIERRA_LFPSFILT_MP_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x8013, SIERRA_SDFILT_H2L_A_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x8009, SIERRA_SDFILT_L2H_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const struct cdns_sierra_data cdns_map_sierra = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SIERRA_MACRO_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) cdns_pcie_cmn_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) cdns_pcie_ln_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cdns_usb_cmn_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) cdns_usb_ln_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const struct cdns_sierra_data cdns_ti_map_sierra = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) SIERRA_MACRO_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) cdns_pcie_cmn_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) cdns_pcie_ln_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) cdns_usb_cmn_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) cdns_usb_ln_regs_ext_ssc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct of_device_id cdns_sierra_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .compatible = "cdns,sierra-phy-t0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .data = &cdns_map_sierra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .compatible = "ti,sierra-phy-t0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .data = &cdns_ti_map_sierra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static struct platform_driver cdns_sierra_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .probe = cdns_sierra_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .remove = cdns_sierra_phy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .name = "cdns-sierra-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .of_match_table = cdns_sierra_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) module_platform_driver(cdns_sierra_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) MODULE_ALIAS("platform:cdns_sierra");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_AUTHOR("Cadence Design Systems");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MODULE_DESCRIPTION("CDNS sierra phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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