^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Salvo PHY is a 28nm PHY, it is a legacy PHY, and only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * for USB3 and USB2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2019-2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* PHY register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_PMA_CMN_CTRL1 0xC800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TB_ADDR_CMN_PLL0_INTDIV 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TB_ADDR_CMN_PLL0_FRACDIV 0x0095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TB_ADDR_CMN_PLL0_SS_CTRL2 0x0099
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TB_ADDR_CMN_PLL0_DSM_DIAG 0x0097
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TB_ADDR_CMN_DIAG_PLL0_OVRD 0x01c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD 0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD 0x01c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE 0x01C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE 0x01C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TB_ADDR_CMN_DIAG_PLL0_LF_PROG 0x01C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE 0x01c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TB_ADDR_CMN_PSM_CLK_CTRL 0x0061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR 0x40ea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TB_ADDR_XCVR_PSM_RCTRL 0x4001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TB_ADDR_TX_PSC_A0 0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TB_ADDR_TX_PSC_A1 0x4101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TB_ADDR_TX_PSC_A2 0x4102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TB_ADDR_TX_PSC_A3 0x4103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TB_ADDR_TX_DIAG_ECTRL_OVRD 0x41f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TB_ADDR_TX_PSC_CAL 0x4106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TB_ADDR_TX_PSC_RDY 0x4107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TB_ADDR_RX_PSC_A0 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TB_ADDR_RX_PSC_A1 0x8001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TB_ADDR_RX_PSC_A2 0x8002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TB_ADDR_RX_PSC_A3 0x8003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TB_ADDR_RX_PSC_CAL 0x8006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TB_ADDR_RX_PSC_RDY 0x8007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TB_ADDR_TX_TXCC_MGNLS_MULT_000 0x4058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TB_ADDR_RX_SLC_CU_ITER_TMR 0x80e3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TB_ADDR_RX_SIGDET_HL_FILT_TMR 0x8090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TB_ADDR_RX_SAMP_DAC_CTRL 0x8058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TB_ADDR_RX_DIAG_SIGDET_TUNE 0x81dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 0x81df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TB_ADDR_RX_DIAG_BS_TM 0x81f5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TB_ADDR_RX_DIAG_DFE_CTRL1 0x81d3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 0x81c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TB_ADDR_RX_DIAG_ILL_E_TRIM0 0x81c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 0x81c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 0x81c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TB_ADDR_RX_DIAG_RXFE_TM3 0x81f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TB_ADDR_RX_DIAG_RXFE_TM4 0x81f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TB_ADDR_RX_DIAG_LFPSDET_TUNE 0x81dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TB_ADDR_RX_DIAG_DFE_CTRL3 0x81d5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TB_ADDR_RX_DIAG_SC2C_DELAY 0x81e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TB_ADDR_RX_REE_VGA_GAIN_NODFE 0x81bf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TB_ADDR_XCVR_PSM_CAL_TMR 0x4002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TB_ADDR_XCVR_PSM_A0BYP_TMR 0x4004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TB_ADDR_XCVR_PSM_A0IN_TMR 0x4003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TB_ADDR_XCVR_PSM_A1IN_TMR 0x4005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TB_ADDR_XCVR_PSM_A2IN_TMR 0x4006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TB_ADDR_XCVR_PSM_A3IN_TMR 0x4007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TB_ADDR_XCVR_PSM_A4IN_TMR 0x4008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TB_ADDR_XCVR_PSM_A5IN_TMR 0x4009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TB_ADDR_XCVR_PSM_A0OUT_TMR 0x400a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TB_ADDR_XCVR_PSM_A1OUT_TMR 0x400b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TB_ADDR_XCVR_PSM_A2OUT_TMR 0x400c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TB_ADDR_XCVR_PSM_A3OUT_TMR 0x400d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TB_ADDR_XCVR_PSM_A4OUT_TMR 0x400e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TB_ADDR_XCVR_PSM_A5OUT_TMR 0x400f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TB_ADDR_TX_RCVDET_EN_TMR 0x4122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TB_ADDR_TX_RCVDET_ST_TMR 0x4123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TB_ADDR_TX_RCVDETSC_CTRL 0x4124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* TB_ADDR_TX_RCVDETSC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RXDET_IN_P3_32KHZ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct cdns_reg_pairs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct cdns_salvo_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 reg_offset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const struct cdns_reg_pairs *init_sequence_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 init_sequence_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct cdns_salvo_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct cdns_salvo_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct of_device_id cdns_salvo_phy_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return (u16)readl(salvo_phy->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg * (1 << salvo_phy->data->reg_offset_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(val, salvo_phy->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg * (1 << salvo_phy->data->reg_offset_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Below bringup sequence pair are from Cadence PHY's User Guide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * and NXP platform tuning results.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct cdns_reg_pairs cdns_nxp_sequence_pair[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0x0830, PHY_PMA_CMN_CTRL1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0xbefc, TB_ADDR_XCVR_PSM_RCTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x7799, TB_ADDR_TX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x7798, TB_ADDR_TX_PSC_A1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x509b, TB_ADDR_TX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x509b, TB_ADDR_TX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x2090, TB_ADDR_TX_PSC_CAL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x2090, TB_ADDR_TX_PSC_RDY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0xA6FD, TB_ADDR_RX_PSC_A0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0xA6FD, TB_ADDR_RX_PSC_A1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0xA410, TB_ADDR_RX_PSC_A2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x2410, TB_ADDR_RX_PSC_A3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x23FF, TB_ADDR_RX_PSC_CAL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x2010, TB_ADDR_RX_PSC_RDY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x0480, TB_ADDR_RX_DIAG_BS_TM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x8000, TB_ADDR_RX_DIAG_RXFE_TM3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x0003, TB_ADDR_RX_DIAG_RXFE_TM4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Change rx detect parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x0960, TB_ADDR_TX_RCVDET_EN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x01e0, TB_ADDR_TX_RCVDET_ST_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int cdns_salvo_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct cdns_salvo_data *data = salvo_phy->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = clk_prepare_enable(salvo_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (i = 0; i < data->init_sequence_length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) value |= RXDET_IN_P3_32KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) RXDET_IN_P3_32KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clk_disable_unprepare(salvo_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int cdns_salvo_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return clk_prepare_enable(salvo_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int cdns_salvo_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clk_disable_unprepare(salvo_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct phy_ops cdns_salvo_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .init = cdns_salvo_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .power_on = cdns_salvo_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .power_off = cdns_salvo_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int cdns_salvo_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct cdns_salvo_phy *salvo_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct cdns_salvo_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) match = of_match_device(cdns_salvo_phy_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) data = (struct cdns_salvo_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!salvo_phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) salvo_phy->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) salvo_phy->clk = devm_clk_get_optional(dev, "salvo_phy_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (IS_ERR(salvo_phy->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return PTR_ERR(salvo_phy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) salvo_phy->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (IS_ERR(salvo_phy->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return PTR_ERR(salvo_phy->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) salvo_phy->phy = devm_phy_create(dev, NULL, &cdns_salvo_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (IS_ERR(salvo_phy->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return PTR_ERR(salvo_phy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) phy_set_drvdata(salvo_phy->phy, salvo_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct cdns_salvo_data cdns_nxp_salvo_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) cdns_nxp_sequence_pair,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ARRAY_SIZE(cdns_nxp_sequence_pair),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct of_device_id cdns_salvo_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .compatible = "nxp,salvo-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .data = &cdns_nxp_salvo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct platform_driver cdns_salvo_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .probe = cdns_salvo_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "cdns-salvo-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .of_match_table = cdns_salvo_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) module_platform_driver(cdns_salvo_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MODULE_DESCRIPTION("Cadence SALVO PHY Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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