^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright: 2017-2018 Cadence Design Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy-mipi-dphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_WAKEUP_TIME_NS 800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DPHY_PLL_RATE_HZ 108000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* DPHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DPHY_PMA_CMN(reg) (reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DPHY_PMA_LCLK(reg) (0x100 + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DPHY_PMA_RCLK(reg) (0x600 + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DPHY_PCS(reg) (0xb00 + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPHY_CMN_SSM_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DPHY_CMN_TX_MODE_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DPHY_CMN_PWM_DIV(x) ((x) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DPHY_CMN_PWM_LOW(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DPHY_CMN_PWM_HIGH(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DPHY_CMN_IPDIV_FROM_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DPHY_CMN_IPDIV(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DPHY_CMN_OPDIV_FROM_REG BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DPHY_CMN_OPDIV(x) ((x) << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DPHY_PSM_CFG DPHY_PCS(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DPHY_PSM_CFG_FROM_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DPHY_PSM_CLK_DIV(x) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DSI_HBP_FRAME_OVERHEAD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DSI_HSA_FRAME_OVERHEAD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DSI_HFP_FRAME_OVERHEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DSI_BLANKING_FRAME_OVERHEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DSI_NULL_FRAME_OVERHEAD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DSI_EOT_PKT_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct cdns_dphy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 pll_ipdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 pll_opdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u16 pll_fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int nlanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum cdns_dphy_clk_lane_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct cdns_dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct cdns_dphy_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int (*probe)(struct cdns_dphy *dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void (*remove)(struct cdns_dphy *dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum cdns_dphy_clk_lane_cfg cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void (*set_pll_cfg)(struct cdns_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct cdns_dphy_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct cdns_dphy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct cdns_dphy_cfg cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk *psm_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk *pll_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const struct cdns_dphy_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct cdns_dphy_cfg *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct phy_configure_opts_mipi_dphy *opts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int *dsi_hfp_ext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 dlane_bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) memset(cfg, 0, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) else if (pll_ref_hz < 19200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cfg->pll_ipdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) else if (pll_ref_hz < 38400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cfg->pll_ipdiv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else if (pll_ref_hz < 76800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cfg->pll_ipdiv = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) cfg->pll_ipdiv = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dlane_bps = opts->hs_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) else if (dlane_bps >= 1250000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) cfg->pll_opdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else if (dlane_bps >= 630000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) cfg->pll_opdiv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else if (dlane_bps >= 320000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cfg->pll_opdiv = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else if (dlane_bps >= 160000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cfg->pll_opdiv = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cfg->pll_ipdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pll_ref_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long psm_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!psm_clk_hz || psm_clk_hz > 100000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (dphy->ops->set_psm_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dphy->ops->set_psm_div(dphy, psm_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum cdns_dphy_clk_lane_cfg cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (dphy->ops->set_clk_lane_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dphy->ops->set_clk_lane_cfg(dphy, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct cdns_dphy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (dphy->ops->set_pll_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dphy->ops->set_pll_cfg(dphy, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return dphy->ops->get_wakeup_time_ns(dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Default wakeup time is 800 ns (in a simulated environment). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const struct cdns_dphy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 fbdiv_low, fbdiv_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fbdiv_low = (cfg->pll_fbdiv / 4) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DPHY_CMN_IPDIV(cfg->pll_ipdiv) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DPHY_CMN_OPDIV(cfg->pll_opdiv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dphy->regs + DPHY_CMN_OPIPDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(DPHY_CMN_FBDIV_FROM_REG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dphy->regs + DPHY_CMN_FBDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DPHY_CMN_PWM_DIV(0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dphy->regs + DPHY_CMN_PWM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dphy->regs + DPHY_PSM_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * This is the reference implementation of DPHY hooks. Specific integration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * this IP may have to re-implement some of them depending on how they decided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * to wire things in the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct cdns_dphy_ops ref_dphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .set_pll_cfg = cdns_dphy_ref_set_pll_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .set_psm_div = cdns_dphy_ref_set_psm_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int cdns_dphy_config_from_opts(struct phy *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct phy_configure_opts_mipi_dphy *opts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct cdns_dphy_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct cdns_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int dsi_hfp_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = phy_mipi_dphy_config_validate(opts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = cdns_dsi_get_dphy_pll_cfg(dphy, cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) opts, &dsi_hfp_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct cdns_dphy_cfg cfg = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (mode != PHY_MODE_MIPI_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct cdns_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct cdns_dphy_cfg cfg = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Configure the internal PSM clk divider so that the DPHY has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * 1MHz clk (or something close).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = cdns_dphy_setup_psm(dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * and 8 data lanes, each clk lane can be attache different set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * data lanes. The 2 groups are named 'left' and 'right', so here we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * just say that we want the 'left' clk lane to drive the 'left' data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * lanes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Configure the DPHY PLL that will be used to generate the TX byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * clk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cdns_dphy_set_pll_cfg(dphy, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int cdns_dphy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct cdns_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clk_prepare_enable(dphy->psm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_prepare_enable(dphy->pll_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Start TX state machine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dphy->regs + DPHY_CMN_SSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int cdns_dphy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct cdns_dphy *dphy = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) clk_disable_unprepare(dphy->pll_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) clk_disable_unprepare(dphy->psm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct phy_ops cdns_dphy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .configure = cdns_dphy_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .validate = cdns_dphy_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .power_on = cdns_dphy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .power_off = cdns_dphy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int cdns_dphy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cdns_dphy *dphy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!dphy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_set_drvdata(&pdev->dev, dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dphy->ops = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!dphy->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dphy->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (IS_ERR(dphy->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return PTR_ERR(dphy->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dphy->psm_clk = devm_clk_get(&pdev->dev, "psm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (IS_ERR(dphy->psm_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return PTR_ERR(dphy->psm_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (IS_ERR(dphy->pll_ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return PTR_ERR(dphy->pll_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (dphy->ops->probe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = dphy->ops->probe(dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (IS_ERR(dphy->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(&pdev->dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (dphy->ops->remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dphy->ops->remove(dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return PTR_ERR(dphy->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) phy_set_drvdata(dphy->phy, dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) phy_provider = devm_of_phy_provider_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int cdns_dphy_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (dphy->ops->remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dphy->ops->remove(dphy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct of_device_id cdns_dphy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { .compatible = "cdns,dphy", .data = &ref_dphy_ops },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct platform_driver cdns_dphy_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .probe = cdns_dphy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .remove = cdns_dphy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "cdns-mipi-dphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .of_match_table = cdns_dphy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) module_platform_driver(cdns_dphy_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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