^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This module contains USB PHY initialization for power up and S3 resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/soc/brcmstb/brcmstb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "phy-brcm-usb-init.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHY_PORTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PHY_PORT_SELECT_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PHY_PORT_SELECT_1 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Register definitions for the USB CTRL block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USB_CTRL_SETUP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define USB_CTRL_SETUP_IOC_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define USB_CTRL_SETUP_IPP_MASK 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USB_CTRL_SETUP_BABO_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USB_CTRL_SETUP_FNHW_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USB_CTRL_SETUP_FNBO_MASK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define USB_CTRL_SETUP_WABO_MASK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK 0x00002000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USB_CTRL_SETUP_SCB1_EN_MASK 0x00004000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define USB_CTRL_SETUP_SCB2_EN_MASK 0x00008000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK 0X00020000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK 0x00010000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define USB_CTRL_SETUP_STRAP_IPP_SEL_MASK 0x02000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK 0x04000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define USB_CTRL_SETUP_OC3_DISABLE_MASK 0xc0000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define USB_CTRL_PLL_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define USB_CTRL_PLL_CTL_PLL_RESETB_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK 0x80000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define USB_CTRL_EBRIDGE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK 0x00020000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK 0x00000f80 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USB_CTRL_OBRIDGE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USB_CTRL_MDIO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define USB_CTRL_MDIO2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define USB_CTRL_UTMI_CTL_1 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USB_CTRL_USB_PM 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK 0x00800000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK 0x00400000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK 0x40000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USB_CTRL_USB_PM_USB_PWRDN_MASK 0x80000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB_CTRL_USB_PM_SOFT_RESET_MASK 0x40000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USB_CTRL_USB_PM_USB20_HC_RESETB_MASK 0x30000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK 0x00300000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB_CTRL_USB_PM_RMTWKUP_EN_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USB_CTRL_USB_PM_STATUS 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define USB_CTRL_USB30_CTL1 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK 0x00020000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define USB_CTRL_USB30_CTL1_USB3_IOC_MASK 0x10000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USB_CTRL_USB30_CTL1_USB3_IPP_MASK 0x20000000 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USB_CTRL_USB30_PCTL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USB_CTRL_USB_DEVICE_CTL1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK 0x00000003 /* option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Register definitions for the XHCI EC block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB_XHCI_EC_IRAADR 0x658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USB_XHCI_EC_IRADAT 0x65c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum brcm_family_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) BRCM_FAMILY_3390A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BRCM_FAMILY_7250B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BRCM_FAMILY_7271A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) BRCM_FAMILY_7364A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) BRCM_FAMILY_7366C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) BRCM_FAMILY_74371A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) BRCM_FAMILY_7439B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) BRCM_FAMILY_7445D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BRCM_FAMILY_7260A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BRCM_FAMILY_7278A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) BRCM_FAMILY_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define USB_BRCM_FAMILY(chip) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [BRCM_FAMILY_##chip] = __stringify(chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char *family_names[BRCM_FAMILY_COUNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) USB_BRCM_FAMILY(3390A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) USB_BRCM_FAMILY(7250B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) USB_BRCM_FAMILY(7271A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) USB_BRCM_FAMILY(7364A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) USB_BRCM_FAMILY(7366C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) USB_BRCM_FAMILY(74371A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) USB_BRCM_FAMILY(7439B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) USB_BRCM_FAMILY(7445D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) USB_BRCM_FAMILY(7260A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) USB_BRCM_FAMILY(7278A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) USB_CTRL_SETUP_SCB1_EN_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) USB_CTRL_SETUP_SCB2_EN_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) USB_CTRL_USB_PM_SOFT_RESET_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) USB_CTRL_SETUP_ENDIAN_SELECTOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) USB_CTRL_SELECTOR_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define USB_CTRL_MASK_FAMILY(params, reg, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define USB_CTRL_SET_FAMILY(params, reg, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) usb_ctrl_set_family(params, USB_CTRL_##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) USB_CTRL_##reg##_##field##_SELECTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USB_CTRL_UNSET_FAMILY(params, reg, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) usb_ctrl_unset_family(params, USB_CTRL_##reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) USB_CTRL_##reg##_##field##_SELECTOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MDIO_USB2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MDIO_USB3 BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define USB_CTRL_SETUP_ENDIAN_BITS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) USB_CTRL_MASK(SETUP, BABO) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) USB_CTRL_MASK(SETUP, FNHW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) USB_CTRL_MASK(SETUP, FNBO) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) USB_CTRL_MASK(SETUP, WABO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ENDIAN_SETTINGS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) USB_CTRL_MASK(SETUP, BABO) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) USB_CTRL_MASK(SETUP, FNHW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ENDIAN_SETTINGS ( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) USB_CTRL_MASK(SETUP, FNHW) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) USB_CTRL_MASK(SETUP, FNBO) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) USB_CTRL_MASK(SETUP, WABO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct id_to_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct id_to_type id_to_type_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x33900000, BRCM_FAMILY_3390A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x72500010, BRCM_FAMILY_7250B0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x72600000, BRCM_FAMILY_7260A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x72550000, BRCM_FAMILY_7260A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0x72680000, BRCM_FAMILY_7271A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x72710000, BRCM_FAMILY_7271A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0x73640000, BRCM_FAMILY_7364A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x73660020, BRCM_FAMILY_7366C0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x07437100, BRCM_FAMILY_74371A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x74390010, BRCM_FAMILY_7439B0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x74450030, BRCM_FAMILY_7445D0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x72780000, BRCM_FAMILY_7278A0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0, BRCM_FAMILY_7271A0 }, /* default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* 3390B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [BRCM_FAMILY_3390A0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) USB_CTRL_USB_PM_USB_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* 7250b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [BRCM_FAMILY_7250B0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 7271a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [BRCM_FAMILY_7271A0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) USB_CTRL_USB_PM_USB_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) USB_CTRL_USB_PM_SOFT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* 7364a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [BRCM_FAMILY_7364A0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* 7366c0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [BRCM_FAMILY_7366C0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) USB_CTRL_USB_PM_USB_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* 74371A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [BRCM_FAMILY_74371A0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* 7439B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) [BRCM_FAMILY_7439B0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) USB_CTRL_USB_PM_USB_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* 7445d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [BRCM_FAMILY_7445D0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) USB_CTRL_SETUP_SCB1_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) USB_CTRL_SETUP_SCB2_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* 7260a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [BRCM_FAMILY_7260A0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) USB_CTRL_USB_PM_USB_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) USB_CTRL_USB_PM_SOFT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* 7278a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [BRCM_FAMILY_7278A0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) USB_CTRL_SETUP_OC3_DISABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) USB_CTRL_USB_PM_USB_PWRDN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) USB_CTRL_USB_PM_SOFT_RESET_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0, /* USB_CTRL_SETUP ENDIAN bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) void usb_ctrl_unset_family(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 reg_offset, u32 field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mask = params->usb_reg_bits_map[field];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) void usb_ctrl_set_family(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 reg_offset, u32 field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mask = params->usb_reg_bits_map[field];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) data = (reg << 16) | mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) data |= (1 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) data &= ~(1 << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* wait for the 60MHz parallel to serial shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* wait for the 60MHz parallel to serial shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return brcm_usb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 val, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) data = (reg << 16) | val | mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) data |= (1 << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) data &= ~(1 << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* wait for the 60MHz parallel to serial shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* wait for the 60MHz parallel to serial shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* first disable FSM but also leave it that way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* to allow normal suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* reset USB 2.0 PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* PLL reset period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Give PLL enough time to lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Increase USB 2.0 TX level to meet spec requirement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Set correct window for PLL lock detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Re-enable USB 3.0 pipe reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 val, ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (ii = 0; ii < PHY_PORTS; ++ii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Set correct default for sigdet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val = (val & ~0x800f) | 0x800d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ofs = PHY_PORT_SELECT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 val, ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) for (ii = 0; ii < PHY_PORTS; ++ii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Set correct default for SKIP align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ofs = PHY_PORT_SELECT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 val, ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for (ii = 0; ii < PHY_PORTS; ++ii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Let EQ freeze after TSEQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) val &= ~0x0008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ofs = PHY_PORT_SELECT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * On newer B53 based SoC's, the reference clock for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * 3.0 PLL has been changed from 50MHz to 54MHz so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * PLL needs to be reprogrammed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * See SWLINUX-4006.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * On the 7364C0, the reference clock for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * 3.0 PLL has been changed from 50MHz to 54MHz to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * work around a MOCA issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * See SWLINUX-4169.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) switch (params->selected_family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case BRCM_FAMILY_3390A0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case BRCM_FAMILY_7250B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case BRCM_FAMILY_7366C0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case BRCM_FAMILY_74371A0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case BRCM_FAMILY_7439B0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case BRCM_FAMILY_7445D0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case BRCM_FAMILY_7260A0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case BRCM_FAMILY_7364A0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (BRCM_REV(params->family_id) < 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* set USB 3.0 PLL to accept 54Mhz reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* both ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) for (ii = 0; ii < PHY_PORTS; ++ii) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ofs = PHY_PORT_SELECT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* restart PLL sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Give PLL enough time to lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Enable USB 3.0 TX spread spectrum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * which should have been adequate. However, due to a bug in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) brcmusb_usb3_pll_fix(ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) brcmusb_usb3_pll_54mhz(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) brcmusb_usb3_ssc_enable(ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) brcmusb_usb3_enable_pipe_reset(ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) brcmusb_usb3_enable_sigdet(ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) brcmusb_usb3_enable_skip_align(ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) brcmusb_usb3_unfreeze_aeq(ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static void brcmusb_memc_fix(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 prid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (params->selected_family != BRCM_FAMILY_7445D0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * This is a workaround for HW7445-1869 where a DMA write ends up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * doing a read pre-fetch after the end of the DMA buffer. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * causes a problem when the DMA buffer is at the end of physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * memory, causing the pre-fetch read to access non-existent memory,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * and the chip bondout has MEMC2 disabled. When the pre-fetch read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * tries to use the disabled MEMC2, it hangs the bus. The workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * is to disable MEMC2 access in the usb controller which avoids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * the hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) prid = params->product_id & 0xfffff000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) switch (prid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case 0x72520000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case 0x74480000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case 0x74490000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case 0x07252000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) case 0x07448000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case 0x07449000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) void __iomem *xhci_ec_base = params->regs[BRCM_REGS_XHCI_EC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (params->family_id != 0x74371000 || !xhci_ec_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) brcm_usb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = brcm_usb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* set cfg_pick_ss_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val |= (1 << 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) brcm_usb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Reset USB 3.0 PHY for workaround to take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) USB_CTRL_UNSET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (on_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) USB_CTRL_UNSET_FAMILY(params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) USB30_CTL1, XHC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) } else { /* De-assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) USB_CTRL_SET_FAMILY(params, USB30_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) XHC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Return the best map table family. The order is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * - exact match of chip and major rev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * - exact match of chip and closest older major rev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * - default chip/rev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * NOTE: The minor rev is always ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static enum brcm_family_type get_family_type(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int last_type = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 last_family = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 family_no_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) family = params->family_id & 0xfffffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) family_no_major = params->family_id & 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) for (x = 0; id_to_type_table[x].id; x++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (family == id_to_type_table[x].id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return id_to_type_table[x].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (family_no_major == (id_to_type_table[x].id & 0xffffff00))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (family > id_to_type_table[x].id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) last_family < id_to_type_table[x].id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) last_family = id_to_type_table[x].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) last_type = id_to_type_table[x].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* If no match, return the default family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (last_type == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return id_to_type_table[x].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return last_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static void usb_init_ipp(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u32 orig_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Starting with the 7445d0, there are no longer separate 3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * versions of IOC and IPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (params->ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (params->ipp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) orig_reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Never use the strap, it's going away. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) reg &= ~(USB_CTRL_MASK_FAMILY(params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) STRAP_CC_DRD_MODE_ENABLE_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* override ipp strap pin (if it exits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (params->ipp != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) STRAP_IPP_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Override the default OC and PP polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (params->ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) reg |= USB_CTRL_MASK(SETUP, IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (params->ipp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) reg |= USB_CTRL_MASK(SETUP, IPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * If we're changing IPP, make sure power is off long enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * to turn off any connected devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if ((reg ^ orig_reg) & USB_CTRL_MASK(SETUP, IPP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static void usb_wake_enable(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) USB_CTRL_SET(ctrl, USB_PM, RMTWKUP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) USB_CTRL_UNSET(ctrl, USB_PM, RMTWKUP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void usb_init_common(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Clear any pending wake conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) usb_wake_enable(params, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_PM_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_PM_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Take USB out of power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* 1 millisecond - for USB clocks to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* 1 millisecond - for USB clocks to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (params->selected_family != BRCM_FAMILY_74371A0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (BRCM_ID(params->family_id) != 0x7364))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * HW7439-637: 7439a0 and its derivatives do not have large
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * enough descriptor storage for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Block auto PLL suspend by USB2 PHY (Sasi) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (params->selected_family == BRCM_FAMILY_7364A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Suppress overcurrent indication from USB30 ports for A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) brcmusb_usb_phy_ldo_fix(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) brcmusb_usb2_eye_fix(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Make sure the the second and third memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * interfaces are enabled if they exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) brcmusb_memc_fix(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) reg |= params->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) switch (params->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case USB_CTLR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (params->mode == USB_CTLR_MODE_TYPEC_PD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) USB_CTRL_UNSET_FAMILY(params, SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) CC_DRD_MODE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void usb_init_eohci(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (params->selected_family == BRCM_FAMILY_7366C0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * Don't enable this so the memory controller doesn't read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * into memory holes. NOTE: This bit is low true on 7366C0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Setup the endian bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (params->selected_family == BRCM_FAMILY_7271A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Enable LS keep alive fix for certain keyboards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (params->family_id == 0x72550000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * Make the burst size 512 bytes to fix a hardware bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * on the 7255a0. See HW7255-24.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, EBRIDGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) reg &= ~USB_CTRL_MASK(EBRIDGE, EBR_SCB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) reg |= 0x800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, EBRIDGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static void usb_init_xhci(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) USB_CTRL_UNSET(ctrl, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* 1 millisecond - for USB clocks to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (BRCM_ID(params->family_id) == 0x7366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * The PHY3_SOFT_RESETB bits default to the wrong state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Kick start USB3 PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Make sure it's low to insure a rising edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) brcmusb_usb3_phy_workarounds(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) brcmusb_xhci_soft_reset(params, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) brcmusb_usb3_otp_fix(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void usb_uninit_common(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (params->wake_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) usb_wake_enable(params, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static void usb_uninit_eohci(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void usb_uninit_xhci(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) brcmusb_xhci_soft_reset(params, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_PCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PHY3_IDDQ_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int usb_get_dual_select(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) reg |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const struct brcm_usb_init_ops bcm7445_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .init_ipp = usb_init_ipp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .init_common = usb_init_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .init_eohci = usb_init_eohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .init_xhci = usb_init_xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .uninit_common = usb_uninit_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .uninit_eohci = usb_uninit_eohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .uninit_xhci = usb_uninit_xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .get_dual_select = usb_get_dual_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .set_dual_select = usb_set_dual_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int fam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) fam = get_family_type(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) params->selected_family = fam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) params->usb_reg_bits_map =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) &usb_reg_bits_map_table[fam][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) params->family_name = family_names[fam];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) params->ops = &bcm7445_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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