Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2018, Broadcom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This module contains USB PHY initialization for power up and S3 resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * for newer Synopsys based USB hardware first used on the bcm7216.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/soc/brcmstb/brcmstb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "phy-brcm-usb-init.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PHY_LOCK_TIMEOUT_MS 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* Register definitions for syscon piarbctl registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PIARBCTL_CAM			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PIARBCTL_SPLITTER		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PIARBCTL_MISC			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define   PIARBCTL_MISC_SECURE_MASK			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define   PIARBCTL_MISC_USB_SELECT_MASK			0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define   PIARBCTL_MISC_USB_4G_SDRAM_MASK		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define   PIARBCTL_MISC_USB_PRIORITY_MASK		0x000f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define   PIARBCTL_MISC_USB_MEM_PAGE_MASK		0x0000f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define   PIARBCTL_MISC_CAM1_MEM_PAGE_MASK		0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define   PIARBCTL_MISC_CAM0_MEM_PAGE_MASK		0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define   PIARBCTL_MISC_SATA_PRIORITY_MASK		0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PIARBCTL_MISC_USB_ONLY_MASK		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	(PIARBCTL_MISC_USB_SELECT_MASK |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	 PIARBCTL_MISC_USB_4G_SDRAM_MASK |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	 PIARBCTL_MISC_USB_PRIORITY_MASK |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 PIARBCTL_MISC_USB_MEM_PAGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Register definitions for the USB CTRL block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define USB_CTRL_SETUP			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define   USB_CTRL_SETUP_STRAP_IPP_SEL_MASK		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define   USB_CTRL_SETUP_SCB2_EN_MASK			0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define   USB_CTRL_SETUP_tca_drv_sel_MASK		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define   USB_CTRL_SETUP_SCB1_EN_MASK			0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define   USB_CTRL_SETUP_SOFT_SHUTDOWN_MASK		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define   USB_CTRL_SETUP_IPP_MASK			0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define   USB_CTRL_SETUP_IOC_MASK			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define USB_CTRL_USB_PM			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define   USB_CTRL_USB_PM_USB_PWRDN_MASK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   USB_CTRL_USB_PM_SOFT_RESET_MASK		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define USB_CTRL_USB_PM_STATUS		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define USB_CTRL_USB_DEVICE_CTL1	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define   USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK	0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USB_CTRL_TEST_PORT_CTL		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define   USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK	0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define   USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_PME_GEN_MASK	0x0000002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define USB_CTRL_TP_DIAG1		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define   USB_CTLR_TP_DIAG1_wake_MASK	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define USB_CTRL_CTLR_CSHCR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define   USB_CTRL_CTLR_CSHCR_ctl_pme_en_MASK	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* Register definitions for the USB_PHY block in 7211b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define USB_PHY_PLL_CTL			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define   USB_PHY_PLL_CTL_PLL_RESETB_MASK		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define USB_PHY_PLL_LDO_CTL		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define   USB_PHY_PLL_LDO_CTL_AFE_CORERDY_MASK		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define   USB_PHY_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define   USB_PHY_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define USB_PHY_UTMI_CTL_1		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define   USB_PHY_UTMI_CTL_1_POWER_UP_FSM_EN_MASK	0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define   USB_PHY_UTMI_CTL_1_PHY_MODE_MASK		0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define   USB_PHY_UTMI_CTL_1_PHY_MODE_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define USB_PHY_IDDQ			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define   USB_PHY_IDDQ_phy_iddq_MASK			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define USB_PHY_STATUS			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define   USB_PHY_STATUS_pll_lock_MASK			0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Register definitions for the MDIO registers in the DWC2 block of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * the 7211b0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * NOTE: The PHY's MDIO registers are only accessible through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * legacy DesignWare USB controller even though it's not being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define USB_GMDIOCSR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define USB_GMDIOGEN	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* Register definitions for the BDC EC block in 7211b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define BDC_EC_AXIRDA			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define   BDC_EC_AXIRDA_RTS_MASK			0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define   BDC_EC_AXIRDA_RTS_SHIFT			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static void usb_mdio_write_7211b0(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				  uint8_t addr, uint16_t data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	addr &= 0x1f; /* 5-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	brcm_usb_writel(0xffffffff, usb_mdio + USB_GMDIOGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	while (brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & (1<<31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	brcm_usb_writel(0x59020000 | (addr << 18) | data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			usb_mdio + USB_GMDIOGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	while (brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & (1<<31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	brcm_usb_writel(0x00000000, usb_mdio + USB_GMDIOGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	while (brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & (1<<31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static uint16_t __maybe_unused usb_mdio_read_7211b0(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct brcm_usb_init_params *params, uint8_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	void __iomem *usb_mdio = params->regs[BRCM_REGS_USB_MDIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	addr &= 0x1f; /* 5-bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	brcm_usb_writel(0xffffffff, usb_mdio + USB_GMDIOGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	while (brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & (1<<31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	brcm_usb_writel(0x69020000 | (addr << 18), usb_mdio + USB_GMDIOGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	while (brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & (1<<31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	brcm_usb_writel(0x00000000, usb_mdio + USB_GMDIOGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	while (brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & (1<<31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return brcm_usb_readl(usb_mdio + USB_GMDIOCSR) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void usb2_eye_fix_7211b0(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	/* select bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	usb_mdio_write_7211b0(params, 0x1f, 0x80a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* Set the eye */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	usb_mdio_write_7211b0(params, 0x0a, 0xc6a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void xhci_soft_reset(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			int on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (on_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		USB_CTRL_UNSET(ctrl, USB_PM, XHC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* De-assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		USB_CTRL_SET(ctrl, USB_PM, XHC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void usb_init_ipp(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u32 orig_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	orig_reg = reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (params->ipp != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		/* override ipp strap pin (if it exits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		reg &= ~(USB_CTRL_MASK(SETUP, STRAP_IPP_SEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Override the default OC and PP polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (params->ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		reg |= USB_CTRL_MASK(SETUP, IOC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (params->ipp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		reg |= USB_CTRL_MASK(SETUP, IPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * If we're changing IPP, make sure power is off long enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * to turn off any connected devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if ((reg ^ orig_reg) & USB_CTRL_MASK(SETUP, IPP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void syscon_piarbctl_init(struct regmap *rmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Switch from legacy USB OTG controller to new STB USB controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	regmap_update_bits(rmap, PIARBCTL_MISC, PIARBCTL_MISC_USB_ONLY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			   PIARBCTL_MISC_USB_SELECT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			   PIARBCTL_MISC_USB_4G_SDRAM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void usb_init_common(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	USB_CTRL_UNSET(ctrl, USB_PM, USB_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* 1 millisecond - for USB clocks to settle down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		reg &= ~USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		reg |= params->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	switch (params->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	case USB_CTLR_MODE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		USB_CTRL_UNSET(ctrl, USB_PM, BDC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		USB_CTRL_UNSET(ctrl, USB_PM, BDC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		USB_CTRL_SET(ctrl, USB_PM, BDC_SOFT_RESETB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void usb_wake_enable_7211b0(struct brcm_usb_init_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				   bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		USB_CTRL_SET(ctrl, CTLR_CSHCR, ctl_pme_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		USB_CTRL_UNSET(ctrl, CTLR_CSHCR, ctl_pme_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void usb_init_common_7211b0(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	void __iomem *usb_phy = params->regs[BRCM_REGS_USB_PHY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	void __iomem *bdc_ec = params->regs[BRCM_REGS_BDC_EC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int timeout_ms = PHY_LOCK_TIMEOUT_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (params->syscon_piarbctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		syscon_piarbctl_init(params->syscon_piarbctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	USB_CTRL_UNSET(ctrl, USB_PM, USB_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	usb_wake_enable_7211b0(params, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (!params->wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		/* undo possible suspend settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		brcm_usb_writel(0, usb_phy + USB_PHY_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		reg = brcm_usb_readl(usb_phy + USB_PHY_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		reg |= USB_PHY_PLL_CTL_PLL_RESETB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		brcm_usb_writel(reg, usb_phy + USB_PHY_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		/* temporarily enable FSM so PHY comes up properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		reg = brcm_usb_readl(usb_phy + USB_PHY_UTMI_CTL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		reg |= USB_PHY_UTMI_CTL_1_POWER_UP_FSM_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		brcm_usb_writel(reg, usb_phy + USB_PHY_UTMI_CTL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* Init the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	reg = USB_PHY_PLL_LDO_CTL_AFE_CORERDY_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		USB_PHY_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		USB_PHY_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	brcm_usb_writel(reg, usb_phy + USB_PHY_PLL_LDO_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* wait for lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	while (timeout_ms-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		reg = brcm_usb_readl(usb_phy + USB_PHY_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		if (reg & USB_PHY_STATUS_pll_lock_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Set the PHY_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	reg = brcm_usb_readl(usb_phy + USB_PHY_UTMI_CTL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	reg &= ~USB_PHY_UTMI_CTL_1_PHY_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	reg |= params->mode << USB_PHY_UTMI_CTL_1_PHY_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	brcm_usb_writel(reg, usb_phy + USB_PHY_UTMI_CTL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	usb_init_common(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * The BDC controller will get occasional failures with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * the default "Read Transaction Size" of 6 (1024 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * Set it to 4 (256 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if ((params->mode != USB_CTLR_MODE_HOST) && bdc_ec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		reg = brcm_usb_readl(bdc_ec + BDC_EC_AXIRDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		reg &= ~BDC_EC_AXIRDA_RTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		reg |= (0x4 << BDC_EC_AXIRDA_RTS_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		brcm_usb_writel(reg, bdc_ec + BDC_EC_AXIRDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * Disable FSM, otherwise the PHY will auto suspend when no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * device is connected and will be reset on resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	reg = brcm_usb_readl(usb_phy + USB_PHY_UTMI_CTL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	reg &= ~USB_PHY_UTMI_CTL_1_POWER_UP_FSM_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	brcm_usb_writel(reg, usb_phy + USB_PHY_UTMI_CTL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	usb2_eye_fix_7211b0(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void usb_init_xhci(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	xhci_soft_reset(params, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void usb_uninit_common(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	USB_CTRL_SET(ctrl, USB_PM, USB_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void usb_uninit_common_7211b0(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	void __iomem *usb_phy = params->regs[BRCM_REGS_USB_PHY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (params->wake_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		USB_CTRL_SET(ctrl, TEST_PORT_CTL, TPOUT_SEL_PME_GEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		usb_wake_enable_7211b0(params, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		USB_CTRL_SET(ctrl, USB_PM, USB_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		brcm_usb_writel(0, usb_phy + USB_PHY_PLL_LDO_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		reg = brcm_usb_readl(usb_phy + USB_PHY_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		reg &= ~USB_PHY_PLL_CTL_PLL_RESETB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		brcm_usb_writel(reg, usb_phy + USB_PHY_PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		brcm_usb_writel(USB_PHY_IDDQ_phy_iddq_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				usb_phy + USB_PHY_IDDQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void usb_uninit_xhci(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (!params->wake_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		xhci_soft_reset(params, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int usb_get_dual_select(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	reg &= USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	reg &= ~USB_CTRL_MASK(USB_DEVICE_CTL1, PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	reg |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct brcm_usb_init_ops bcm7216_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.init_ipp = usb_init_ipp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.init_common = usb_init_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.init_xhci = usb_init_xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.uninit_common = usb_uninit_common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.uninit_xhci = usb_uninit_xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.get_dual_select = usb_get_dual_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	.set_dual_select = usb_set_dual_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const struct brcm_usb_init_ops bcm7211b0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.init_ipp = usb_init_ipp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.init_common = usb_init_common_7211b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.init_xhci = usb_init_xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.uninit_common = usb_uninit_common_7211b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.uninit_xhci = usb_uninit_xhci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.get_dual_select = usb_get_dual_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.set_dual_select = usb_set_dual_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void brcm_usb_dvr_init_7216(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	params->family_name = "7216";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	params->ops = &bcm7216_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void brcm_usb_dvr_init_7211b0(struct brcm_usb_init_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	pr_debug("%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	params->family_name = "7211";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	params->ops = &bcm7211b0_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	params->suspend_with_clocks = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }