^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom SATA3 AHCI Controller PHY Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SATA_PCB_BANK_OFFSET 0x23c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX_PORTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Register offset between PHYs in PCB space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* The older SATA PHY registers duplicated per port registers within the map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * rather than having a separate map per port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Register offset between PHYs in PHY control space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum brcm_sata_phy_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) BRCM_SATA_PHY_STB_16NM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) BRCM_SATA_PHY_STB_28NM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) BRCM_SATA_PHY_STB_40NM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) BRCM_SATA_PHY_IPROC_NS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) BRCM_SATA_PHY_IPROC_NSP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) BRCM_SATA_PHY_IPROC_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BRCM_SATA_PHY_DSL_28NM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum brcm_sata_phy_rxaeq_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) RXAEQ_MODE_OFF = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) RXAEQ_MODE_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) RXAEQ_MODE_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!strcmp(m, "auto"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return RXAEQ_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) else if (!strcmp(m, "manual"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return RXAEQ_MODE_MANUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return RXAEQ_MODE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct brcm_sata_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int portnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct brcm_sata_phy *phy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) bool ssc_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) enum brcm_sata_phy_rxaeq_mode rxaeq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 rxaeq_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct brcm_sata_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *ctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum brcm_sata_phy_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct brcm_sata_port phys[MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enum sata_phy_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) BLOCK0_REG_BANK = 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) BLOCK0_XGXSSTATUS = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BLOCK0_SPARE = 0x8d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PLL_REG_BANK_0 = 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PLLCONTROL_0_FREQ_MONITOR = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PLLCONTROL_0_SEQ_START = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PLL_CAP_CHARGE_TIME = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PLL_VCO_CAL_THRESH = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PLL_CAP_CONTROL = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PLL_FREQ_DET_TIME = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PLL_ACTRL2 = 0x8b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PLL_ACTRL2_SELDIV_MASK = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PLL_ACTRL2_SELDIV_SHIFT = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PLL_ACTRL6 = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PLL1_REG_BANK = 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PLL1_ACTRL2 = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PLL1_ACTRL3 = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PLL1_ACTRL4 = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PLL1_ACTRL5 = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PLL1_ACTRL6 = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PLL1_ACTRL7 = 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PLL1_ACTRL8 = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) TX_REG_BANK = 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) TX_ACTRL0 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) TX_ACTRL0_TXPOL_FLIP = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) TX_ACTRL5 = 0x85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) TX_ACTRL5_SSC_EN = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AEQRX_REG_BANK_0 = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) AEQ_CONTROL1 = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) AEQ_CONTROL1_ENABLE = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) AEQ_CONTROL1_FREEZE = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) AEQ_FRC_EQ = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) AEQ_FRC_EQ_FORCE = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AEQ_FRC_EQ_FORCE_VAL = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) AEQ_RFZ_FRC_VAL = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AEQRX_REG_BANK_1 = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) AEQRX_SLCAL0_CTRL0 = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) AEQRX_SLCAL1_CTRL0 = 0x86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) OOB_REG_BANK = 0x150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) OOB1_REG_BANK = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) OOB_CTRL1 = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) OOB_CTRL1_BURST_MAX_MASK = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) OOB_CTRL1_BURST_MAX_SHIFT = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OOB_CTRL1_BURST_MIN_MASK = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) OOB_CTRL1_BURST_MIN_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) OOB_CTRL2 = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) OOB_CTRL2_SEL_ENA_SHIFT = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) OOB_CTRL2_SEL_ENA_RC_SHIFT = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) OOB_CTRL2_BURST_CNT_MASK = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) OOB_CTRL2_BURST_CNT_SHIFT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) TXPMD_REG_BANK = 0x1a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) TXPMD_CONTROL1 = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) RXPMD_REG_BANK = 0x1c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RXPMD_RX_CDR_CONTROL1 = 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) RXPMD_RX_PPM_VAL_MASK = 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) RXPMD_RXPMD_EN_FRC = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RXPMD_RXPMD_EN_FRC_VAL = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RXPMD_RX_CDR_CDR_PROP_BW = 0x82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RXPMD_G_CDR_PROP_BW_MASK = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) RXPMD_G1_CDR_PROP_BW_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RXPMD_G2_CDR_PROP_BW_SHIFT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) RXPMD_G3_CDR_PROB_BW_SHIFT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) RXPMD_G_CDR_ACQ_INT_BW_MASK = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) RXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) RXPMD_G2_CDR_ACQ_INT_BW_SHIFT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) RXPMD_G3_CDR_ACQ_INT_BW_SHIFT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) RXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RXPMD_G_CDR_LOCK_INT_BW_MASK = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RXPMD_G2_CDR_LOCK_INT_BW_SHIFT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) RXPMD_G3_CDR_LOCK_INT_BW_SHIFT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RXPMD_RX_FREQ_MON_CONTROL1 = 0x87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RXPMD_MON_CORRECT_EN = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RXPMD_MON_MARGIN_VAL_MASK = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) enum sata_phy_ctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PHY_CTRL_1 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PHY_CTRL_1_RESET = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct brcm_sata_phy *priv = port->phy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) switch (priv->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case BRCM_SATA_PHY_IPROC_NS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(priv->dev, "invalid phy version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return priv->ctrl_base + (port->portnum * size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void brcm_sata_phy_wr(struct brcm_sata_port *port, u32 bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 ofs, u32 msk, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct brcm_sata_phy *priv = port->phy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void __iomem *pcb_base = priv->phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (priv->version == BRCM_SATA_PHY_STB_40NM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp = (tmp & msk) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static u32 brcm_sata_phy_rd(struct brcm_sata_port *port, u32 bank, u32 ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct brcm_sata_phy *priv = port->phy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void __iomem *pcb_base = priv->phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (priv->version == BRCM_SATA_PHY_STB_40NM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* These defaults were characterized by H/W group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define STB_FMIN_VAL_DEFAULT 0x3df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define STB_FMAX_VAL_DEFAULT 0x3df
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define STB_FMAX_VAL_SSC 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct brcm_sata_phy *priv = port->phy_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* override the TX spread spectrum setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* set fixed min freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) STB_FMIN_VAL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* set fixed max freq depending on SSC config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (port->ssc_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tmp = STB_FMAX_VAL_SSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tmp = STB_FMAX_VAL_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AEQ_FRC_EQ_VAL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define AEQ_FRC_EQ_VAL_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 tmp = 0, reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (port->rxaeq_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case RXAEQ_MODE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case RXAEQ_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg = AEQ_CONTROL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case RXAEQ_MODE_MANUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) reg = AEQ_FRC_EQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int brcm_stb_sata_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) brcm_stb_sata_ssc_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return brcm_stb_sata_rxaeq_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 tmp, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Reduce CP tail current to 1/16th of its default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Turn off CP tail current boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Set a specific AEQ equalizer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ~(tmp | AEQ_RFZ_FRC_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Set RX PPM val center frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (port->ssc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) value = 0x52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ~RXPMD_RX_PPM_VAL_MASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Set proportional loop bandwith Gen1/2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G2_CDR_PROP_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G3_CDR_PROB_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (port->ssc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) value = 2 << RXPMD_G1_CDR_PROP_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 2 << RXPMD_G2_CDR_PROP_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 2 << RXPMD_G3_CDR_PROB_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (port->ssc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) value = 1 << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 1 << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ~tmp, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (port->ssc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) value = 1 << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 1 << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ~tmp, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Set no guard band and clamp CDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (port->ssc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) value = 0x51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ~tmp, RXPMD_MON_CORRECT_EN | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Turn on/off SSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return brcm_stb_sata_16nm_ssc_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* NS2 SATA PLL1 defaults were characterized by H/W group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define NS2_PLL1_ACTRL2_MAGIC 0x1df8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define NS2_PLL1_ACTRL3_MAGIC 0x2b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define NS2_PLL1_ACTRL4_MAGIC 0x8824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int brcm_ns2_sata_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct device *dev = port->phy_priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Configure OOB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Configure PHY PLL register bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) val = NS2_PLL1_ACTRL2_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val = NS2_PLL1_ACTRL3_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val = NS2_PLL1_ACTRL4_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Configure PHY BLOCK0 register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Set oob_clk_sel to refclk/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) brcm_sata_phy_wr(port, BLOCK0_REG_BANK, BLOCK0_SPARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Strobe PHY reset using PHY control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) writel(0x0, ctrl_base + PHY_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Wait for PHY PLL lock by polling pll_lock bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) try = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) while (try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BLOCK0_XGXSSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) try--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* PLL did not lock; give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(dev, "port%d PLL did not lock\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_dbg(dev, "port%d initialized\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int brcm_nsp_sata_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct device *dev = port->phy_priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int oob_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int val, try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Configure OOB control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (port->portnum == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) oob_bank = OOB_REG_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else if (port->portnum == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) oob_bank = OOB1_REG_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0x0c << PLL_ACTRL2_SELDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0xff0, 0x4f0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ~val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) val = PLLCONTROL_0_SEQ_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ~val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ~val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Wait for pll_seq_done bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) try = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) while (--try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BLOCK0_XGXSSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* PLL did not lock; give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(dev, "port%d PLL did not lock\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_dbg(dev, "port%d initialized\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* SR PHY PLL0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SR_PLL0_ACTRL6_MAGIC 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* SR PHY PLL1 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SR_PLL1_ACTRL2_MAGIC 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SR_PLL1_ACTRL3_MAGIC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SR_PLL1_ACTRL4_MAGIC 0x3e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int brcm_sr_sata_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct device *dev = port->phy_priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int val, try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Configure PHY PLL register bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val = SR_PLL1_ACTRL2_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) val = SR_PLL1_ACTRL3_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = SR_PLL1_ACTRL4_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Configure PHY PLL register bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) val = SR_PLL0_ACTRL6_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Wait for PHY PLL lock by polling pll_lock bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) try = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) BLOCK0_XGXSSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) try--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } while (try);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* PLL did not lock; give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dev_err(dev, "port%d PLL did not lock\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Invert Tx polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) brcm_sata_phy_wr(port, TX_REG_BANK, TX_ACTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Configure OOB control to handle 100MHz reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int brcm_dsl_sata_init(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct device *dev = port->phy_priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int try;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 0, 0x3089);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 0, 0x3088);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0, 0x3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0, 0x3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Acquire PLL lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) try = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) while (try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) BLOCK0_XGXSSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) try--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!try) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* PLL did not lock; give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(dev, "port%d PLL did not lock\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_dbg(dev, "port%d initialized\n", port->portnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int brcm_sata_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct brcm_sata_port *port = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) switch (port->phy_priv->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case BRCM_SATA_PHY_STB_16NM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rc = brcm_stb_sata_16nm_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case BRCM_SATA_PHY_STB_28NM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case BRCM_SATA_PHY_STB_40NM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rc = brcm_stb_sata_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case BRCM_SATA_PHY_IPROC_NS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) rc = brcm_ns2_sata_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case BRCM_SATA_PHY_IPROC_NSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) rc = brcm_nsp_sata_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case BRCM_SATA_PHY_IPROC_SR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) rc = brcm_sr_sata_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case BRCM_SATA_PHY_DSL_28NM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) rc = brcm_dsl_sata_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 tmp = BIT(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ~tmp, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int brcm_sata_phy_calibrate(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct brcm_sata_port *port = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int rc = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) switch (port->phy_priv->version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) case BRCM_SATA_PHY_STB_28NM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case BRCM_SATA_PHY_STB_40NM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) brcm_stb_sata_calibrate(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const struct phy_ops phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .init = brcm_sata_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .calibrate = brcm_sata_phy_calibrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct of_device_id brcm_sata_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { .compatible = "brcm,bcm7216-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .data = (void *)BRCM_SATA_PHY_STB_16NM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { .compatible = "brcm,bcm7445-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .data = (void *)BRCM_SATA_PHY_STB_28NM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { .compatible = "brcm,bcm7425-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .data = (void *)BRCM_SATA_PHY_STB_40NM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { .compatible = "brcm,iproc-ns2-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { .compatible = "brcm,iproc-nsp-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { .compatible = "brcm,iproc-sr-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .data = (void *)BRCM_SATA_PHY_IPROC_SR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { .compatible = "brcm,bcm63138-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .data = (void *)BRCM_SATA_PHY_DSL_28NM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int brcm_sata_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) const char *rxaeq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct device_node *dn = dev->of_node, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct brcm_sata_phy *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int ret, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (of_get_child_count(dn) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) priv->phy_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (IS_ERR(priv->phy_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return PTR_ERR(priv->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) of_id = of_match_node(brcm_sata_phy_of_match, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) priv->version = (enum brcm_sata_phy_version)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) priv->version = BRCM_SATA_PHY_STB_28NM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "phy-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) priv->ctrl_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (IS_ERR(priv->ctrl_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return PTR_ERR(priv->ctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) for_each_available_child_of_node(dn, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct brcm_sata_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (of_property_read_u32(child, "reg", &id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(dev, "missing reg property in node %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (id >= MAX_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_err(dev, "invalid reg: %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (priv->phys[id].phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(dev, "already registered port %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) port = &priv->phys[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) port->portnum = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) port->phy_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) port->phy = devm_phy_create(dev, child, &phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) port->rxaeq_mode = RXAEQ_MODE_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!of_property_read_string(child, "brcm,rxaeq-mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) &rxaeq_mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) port->rxaeq_mode = rxaeq_to_val(rxaeq_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (port->rxaeq_mode == RXAEQ_MODE_MANUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) of_property_read_u32(child, "brcm,rxaeq-value",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) &port->rxaeq_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (IS_ERR(port->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = PTR_ERR(port->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) phy_set_drvdata(port->phy, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (IS_ERR(provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(dev, "could not register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_info(dev, "registered %d port(s)\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct platform_driver brcm_sata_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .probe = brcm_sata_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .of_match_table = brcm_sata_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .name = "brcm-sata-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) module_platform_driver(brcm_sata_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_DESCRIPTION("Broadcom SATA PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) MODULE_AUTHOR("Marc Carino");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) MODULE_AUTHOR("Brian Norris");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MODULE_ALIAS("platform:phy-brcm-sata");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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