Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * BCM6328 USBH PHY Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2015 Simon Arlott
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Derived from bcm963xx_4.12L.06B_consumer/kernel/linux/arch/mips/bcm963xx/setup.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (C) 2002 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Derived from OpenWrt patches:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright (C) 2013 Jonas Gorski <jonas.gorski@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (C) 2013 Florian Fainelli <f.fainelli@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* USBH control register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) enum usbh_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	USBH_BRT_CONTROL1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	USBH_BRT_CONTROL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	USBH_BRT_STATUS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	USBH_BRT_STATUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	USBH_UTMI_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define   USBH_UC1_DEV_MODE_SEL		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	USBH_TEST_PORT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	USBH_PLL_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define   USBH_PLLC_REFCLKSEL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define   USBH_PLLC_REFCLKSEL_MASK	(0x3 << USBH_PLLC_REFCLKSEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define   USBH_PLLC_CLKSEL_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define   USBH_PLLC_CLKSEL_MASK		(0x3 << USBH_PLLC_CLKSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define   USBH_PLLC_XTAL_PWRDWNB	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define   USBH_PLLC_PLL_PWRDWNB		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define   USBH_PLLC_PLL_CALEN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define   USBH_PLLC_PHYPLL_BYP		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define   USBH_PLLC_PLL_RESET		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define   USBH_PLLC_PLL_IDDQ_PWRDN	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define   USBH_PLLC_PLL_PWRDN_DELAY	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define   USBH_6318_PLLC_PLL_SUSPEND_EN	BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define   USBH_6318_PLLC_PHYPLL_BYP	BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   USBH_6318_PLLC_PLL_RESET	BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define   USBH_6318_PLLC_PLL_IDDQ_PWRDN	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	USBH_SWAP_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define   USBH_SC_OHCI_DATA_SWAP	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define   USBH_SC_OHCI_ENDIAN_SWAP	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define   USBH_SC_OHCI_LOGICAL_ADDR_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define   USBH_SC_EHCI_DATA_SWAP	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define   USBH_SC_EHCI_ENDIAN_SWAP	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define   USBH_SC_EHCI_LOGICAL_ADDR_EN	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define   USBH_SC_USB_DEVICE_SEL	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	USBH_GENERIC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define   USBH_GC_PLL_SUSPEND_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	USBH_FRAME_ADJUST_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	USBH_SETUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define   USBH_S_IOC			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define   USBH_S_IPP			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	USBH_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	USBH_MDIO32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	USBH_USB_SIM_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define   USBH_USC_LADDR_SEL		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__USBH_ENUM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct bcm63xx_usbh_phy_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	long regs[__USBH_ENUM_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* PLLC bits to set/clear for power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 power_pllc_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 power_pllc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* Setup bits to set/clear for power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 setup_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 setup_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* Swap Control bits to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 swapctl_dev_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	/* Test Port Control value to set if non-zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	u32 tpc_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* USB Sim Control bits to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 usc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* UTMI Control 1 bits to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 utmictl1_dev_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct bcm63xx_usbh_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct clk *usbh_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct clk *usb_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	const struct bcm63xx_usbh_phy_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bool device_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct bcm63xx_usbh_phy_variant usbh_bcm6318 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		[USBH_BRT_CONTROL1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		[USBH_BRT_CONTROL2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		[USBH_BRT_STATUS1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		[USBH_BRT_STATUS2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		[USBH_UTMI_CONTROL1] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		[USBH_TEST_PORT_CONTROL] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		[USBH_PLL_CONTROL1] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		[USBH_SWAP_CONTROL] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		[USBH_GENERIC_CONTROL] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		[USBH_FRAME_ADJUST_VALUE] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		[USBH_SETUP] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		[USBH_MDIO] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		[USBH_MDIO32] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		[USBH_USB_SIM_CONTROL] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.power_pllc_clr = USBH_6318_PLLC_PLL_IDDQ_PWRDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.power_pllc_set = USBH_6318_PLLC_PLL_SUSPEND_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.setup_set = USBH_S_IOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.usc_set = USBH_USC_LADDR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct bcm63xx_usbh_phy_variant usbh_bcm6328 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		[USBH_BRT_CONTROL1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		[USBH_BRT_CONTROL2] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		[USBH_BRT_STATUS1] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		[USBH_BRT_STATUS2] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		[USBH_UTMI_CONTROL1] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		[USBH_TEST_PORT_CONTROL] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		[USBH_PLL_CONTROL1] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		[USBH_SWAP_CONTROL] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		[USBH_GENERIC_CONTROL] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		[USBH_FRAME_ADJUST_VALUE] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		[USBH_SETUP] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		[USBH_MDIO] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		[USBH_MDIO32] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		[USBH_USB_SIM_CONTROL] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.setup_set = USBH_S_IOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct bcm63xx_usbh_phy_variant usbh_bcm6358 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		[USBH_BRT_CONTROL1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		[USBH_BRT_CONTROL2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		[USBH_BRT_STATUS1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		[USBH_BRT_STATUS2] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		[USBH_UTMI_CONTROL1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		[USBH_TEST_PORT_CONTROL] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		[USBH_PLL_CONTROL1] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		[USBH_SWAP_CONTROL] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		[USBH_GENERIC_CONTROL] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		[USBH_FRAME_ADJUST_VALUE] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		[USBH_SETUP] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		[USBH_MDIO] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		[USBH_MDIO32] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		[USBH_USB_SIM_CONTROL] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 * The magic value comes for the original vendor BSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * and is needed for USB to work. Datasheet does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * help, so the magic value is used as-is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.tpc_val = 0x1c0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct bcm63xx_usbh_phy_variant usbh_bcm6368 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		[USBH_BRT_CONTROL1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		[USBH_BRT_CONTROL2] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		[USBH_BRT_STATUS1] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		[USBH_BRT_STATUS2] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		[USBH_UTMI_CONTROL1] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		[USBH_TEST_PORT_CONTROL] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		[USBH_PLL_CONTROL1] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		[USBH_SWAP_CONTROL] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		[USBH_GENERIC_CONTROL] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		[USBH_FRAME_ADJUST_VALUE] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		[USBH_SETUP] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		[USBH_MDIO] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		[USBH_MDIO32] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		[USBH_USB_SIM_CONTROL] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.power_pllc_clr = USBH_PLLC_PLL_IDDQ_PWRDN | USBH_PLLC_PLL_PWRDN_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.setup_set = USBH_S_IOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct bcm63xx_usbh_phy_variant usbh_bcm63268 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		[USBH_BRT_CONTROL1] = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		[USBH_BRT_CONTROL2] = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		[USBH_BRT_STATUS1] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		[USBH_BRT_STATUS2] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		[USBH_UTMI_CONTROL1] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		[USBH_TEST_PORT_CONTROL] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		[USBH_PLL_CONTROL1] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		[USBH_SWAP_CONTROL] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		[USBH_GENERIC_CONTROL] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		[USBH_FRAME_ADJUST_VALUE] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		[USBH_SETUP] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		[USBH_MDIO] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		[USBH_MDIO32] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		[USBH_USB_SIM_CONTROL] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.power_pllc_clr = USBH_PLLC_PLL_IDDQ_PWRDN | USBH_PLLC_PLL_PWRDN_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.setup_clr = USBH_S_IPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.setup_set = USBH_S_IOC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline bool usbh_has_reg(struct bcm63xx_usbh_phy *usbh, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return (usbh->variant->regs[reg] >= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static inline u32 usbh_readl(struct bcm63xx_usbh_phy *usbh, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	return __raw_readl(usbh->base + usbh->variant->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline void usbh_writel(struct bcm63xx_usbh_phy *usbh, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			       u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	__raw_writel(value, usbh->base + usbh->variant->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int bcm63xx_usbh_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	ret = clk_prepare_enable(usbh->usbh_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		dev_err(&phy->dev, "unable to enable usbh clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	ret = clk_prepare_enable(usbh->usb_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_err(&phy->dev, "unable to enable usb_ref clock: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		clk_disable_unprepare(usbh->usbh_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = reset_control_reset(usbh->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		dev_err(&phy->dev, "unable to reset device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		clk_disable_unprepare(usbh->usb_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		clk_disable_unprepare(usbh->usbh_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* Configure to work in native CPU endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (usbh_has_reg(usbh, USBH_SWAP_CONTROL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		u32 val = usbh_readl(usbh, USBH_SWAP_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		val |= USBH_SC_EHCI_DATA_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		val &= ~USBH_SC_EHCI_ENDIAN_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		val |= USBH_SC_OHCI_DATA_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		val &= ~USBH_SC_OHCI_ENDIAN_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (usbh->device_mode && usbh->variant->swapctl_dev_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			val |= usbh->variant->swapctl_dev_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		usbh_writel(usbh, USBH_SWAP_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (usbh_has_reg(usbh, USBH_SETUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		u32 val = usbh_readl(usbh, USBH_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		val |= usbh->variant->setup_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		val &= ~usbh->variant->setup_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		usbh_writel(usbh, USBH_SETUP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (usbh_has_reg(usbh, USBH_USB_SIM_CONTROL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		u32 val = usbh_readl(usbh, USBH_USB_SIM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		val |= usbh->variant->usc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		usbh_writel(usbh, USBH_USB_SIM_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (usbh->variant->tpc_val &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	    usbh_has_reg(usbh, USBH_TEST_PORT_CONTROL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		usbh_writel(usbh, USBH_TEST_PORT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			    usbh->variant->tpc_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (usbh->device_mode &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	    usbh_has_reg(usbh, USBH_UTMI_CONTROL1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	    usbh->variant->utmictl1_dev_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		u32 val = usbh_readl(usbh, USBH_UTMI_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		val |= usbh->variant->utmictl1_dev_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		usbh_writel(usbh, USBH_UTMI_CONTROL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int bcm63xx_usbh_phy_power_on(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (usbh_has_reg(usbh, USBH_PLL_CONTROL1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		u32 val = usbh_readl(usbh, USBH_PLL_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		val |= usbh->variant->power_pllc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		val &= ~usbh->variant->power_pllc_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		usbh_writel(usbh, USBH_PLL_CONTROL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int bcm63xx_usbh_phy_power_off(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (usbh_has_reg(usbh, USBH_PLL_CONTROL1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		u32 val = usbh_readl(usbh, USBH_PLL_CONTROL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		val &= ~usbh->variant->power_pllc_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		val |= usbh->variant->power_pllc_clr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		usbh_writel(usbh, USBH_PLL_CONTROL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int bcm63xx_usbh_phy_exit(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	clk_disable_unprepare(usbh->usbh_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	clk_disable_unprepare(usbh->usb_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct phy_ops bcm63xx_usbh_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.exit = bcm63xx_usbh_phy_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.init = bcm63xx_usbh_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.power_off = bcm63xx_usbh_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.power_on = bcm63xx_usbh_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct phy *bcm63xx_usbh_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 					  struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct bcm63xx_usbh_phy *usbh = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	usbh->device_mode = !!args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	return of_phy_simple_xlate(dev, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int __init bcm63xx_usbh_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	struct bcm63xx_usbh_phy	*usbh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	const struct bcm63xx_usbh_phy_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	usbh = devm_kzalloc(dev, sizeof(*usbh), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (!usbh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	variant = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (!variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	usbh->variant = variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	usbh->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	if (IS_ERR(usbh->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		return PTR_ERR(usbh->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	usbh->reset = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (IS_ERR(usbh->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		if (PTR_ERR(usbh->reset) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			dev_err(dev, "failed to get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		return PTR_ERR(usbh->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	usbh->usbh_clk = devm_clk_get_optional(dev, "usbh");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (IS_ERR(usbh->usbh_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		return PTR_ERR(usbh->usbh_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	usbh->usb_ref_clk = devm_clk_get_optional(dev, "usb_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (IS_ERR(usbh->usb_ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return PTR_ERR(usbh->usb_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	phy = devm_phy_create(dev, NULL, &bcm63xx_usbh_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (IS_ERR(phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		return PTR_ERR(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	platform_set_drvdata(pdev, usbh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	phy_set_drvdata(phy, usbh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	phy_provider = devm_of_phy_provider_register(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 						     bcm63xx_usbh_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	if (IS_ERR(phy_provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		dev_err(dev, "failed to register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return PTR_ERR(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	dev_dbg(dev, "Registered BCM63xx USB PHY driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct of_device_id bcm63xx_usbh_phy_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{ .compatible = "brcm,bcm6318-usbh-phy", .data = &usbh_bcm6318 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ .compatible = "brcm,bcm6328-usbh-phy", .data = &usbh_bcm6328 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{ .compatible = "brcm,bcm6358-usbh-phy", .data = &usbh_bcm6358 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ .compatible = "brcm,bcm6362-usbh-phy", .data = &usbh_bcm6368 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{ .compatible = "brcm,bcm6368-usbh-phy", .data = &usbh_bcm6368 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	{ .compatible = "brcm,bcm63268-usbh-phy", .data = &usbh_bcm63268 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_DEVICE_TABLE(of, bcm63xx_usbh_phy_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct platform_driver bcm63xx_usbh_phy_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.name = "bcm63xx-usbh-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		.of_match_table = bcm63xx_usbh_phy_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.probe	= bcm63xx_usbh_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) module_platform_driver(bcm63xx_usbh_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_DESCRIPTION("BCM63xx USBH PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_AUTHOR("Simon Arlott");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL");