^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016-2018 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum bcm_usb_phy_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) BCM_SR_USB_COMBO_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) BCM_SR_USB_HS_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum bcm_usb_phy_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PLL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PHY_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PHY_PLL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* USB PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const u8 bcm_usb_combo_phy_ss[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [PLL_CTRL] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [PHY_CTRL] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const u8 bcm_usb_combo_phy_hs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [PLL_CTRL] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) [PHY_CTRL] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const u8 bcm_usb_hs_phy[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [PLL_CTRL] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [PHY_CTRL] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum pll_ctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PLL_RESETB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SSPLL_SUSPEND_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PLL_SEQ_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PLL_LOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static const u8 u3pll_ctrl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [PLL_RESETB] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [SSPLL_SUSPEND_EN] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [PLL_SEQ_START] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [PLL_LOCK] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HSPLL_PDIV_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HSPLL_PDIV_VAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const u8 u2pll_ctrl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [PLL_RESETB] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [PLL_LOCK] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum bcm_usb_phy_ctrl_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CORERDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PHY_RESETB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PHY_PCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_PCTL_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SSPHY_PCTL_VAL 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const u8 u3phy_ctrl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [PHY_RESETB] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [PHY_PCTL] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const u8 u2phy_ctrl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [CORERDY] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [PHY_RESETB] = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [PHY_PCTL] = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct bcm_usb_phy_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) uint32_t type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) uint32_t version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const u8 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PLL_LOCK_RETRY_COUNT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum bcm_usb_phy_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) USB_HS_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) USB_SS_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define NUM_BCM_SR_USB_COMBO_PHYS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void bcm_usb_reg32_clrbits(void __iomem *addr, uint32_t clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel(readl(addr) & ~clear, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void bcm_usb_reg32_setbits(void __iomem *addr, uint32_t set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(readl(addr) | set, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int bcm_usb_pll_lock_check(void __iomem *addr, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = readl_poll_timeout_atomic(addr, data, (data & bit), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PLL_LOCK_RETRY_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pr_err("%s: FAIL\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int bcm_usb_ss_phy_init(struct bcm_usb_phy_cfg *phy_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void __iomem *regs = phy_cfg->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const u8 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 rd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) offset = phy_cfg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Set pctl with mode and soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rd_data = readl(regs + offset[PHY_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rd_data &= ~(PHY_PCTL_MASK << u3phy_ctrl[PHY_PCTL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) rd_data |= (SSPHY_PCTL_VAL << u3phy_ctrl[PHY_PCTL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(rd_data, regs + offset[PHY_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bcm_usb_reg32_clrbits(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BIT(u3pll_ctrl[SSPLL_SUSPEND_EN]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bcm_usb_reg32_setbits(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) BIT(u3pll_ctrl[PLL_SEQ_START]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bcm_usb_reg32_setbits(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BIT(u3pll_ctrl[PLL_RESETB]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Maximum timeout for PLL reset done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = bcm_usb_pll_lock_check(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) BIT(u3pll_ctrl[PLL_LOCK]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int bcm_usb_hs_phy_init(struct bcm_usb_phy_cfg *phy_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *regs = phy_cfg->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const u8 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) offset = phy_cfg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bcm_usb_reg32_clrbits(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) BIT(u2pll_ctrl[PLL_RESETB]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bcm_usb_reg32_setbits(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BIT(u2pll_ctrl[PLL_RESETB]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = bcm_usb_pll_lock_check(regs + offset[PLL_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) BIT(u2pll_ctrl[PLL_LOCK]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int bcm_usb_phy_reset(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct bcm_usb_phy_cfg *phy_cfg = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __iomem *regs = phy_cfg->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const u8 *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) offset = phy_cfg->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (phy_cfg->type == USB_HS_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) BIT(u2phy_ctrl[CORERDY]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bcm_usb_reg32_setbits(regs + offset[PHY_CTRL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) BIT(u2phy_ctrl[CORERDY]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int bcm_usb_phy_init(struct phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct bcm_usb_phy_cfg *phy_cfg = phy_get_drvdata(phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (phy_cfg->type == USB_SS_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = bcm_usb_ss_phy_init(phy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else if (phy_cfg->type == USB_HS_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = bcm_usb_hs_phy_init(phy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct phy_ops sr_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .init = bcm_usb_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .reset = bcm_usb_phy_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct phy *bcm_usb_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct bcm_usb_phy_cfg *phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int phy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) phy_cfg = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (!phy_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (phy_cfg->version == BCM_SR_USB_COMBO_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) phy_idx = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (WARN_ON(phy_idx > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return phy_cfg[phy_idx].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return phy_cfg->phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int bcm_usb_phy_create(struct device *dev, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *regs, uint32_t version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct bcm_usb_phy_cfg *phy_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (version == BCM_SR_USB_COMBO_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) phy_cfg = devm_kzalloc(dev, NUM_BCM_SR_USB_COMBO_PHYS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) sizeof(struct bcm_usb_phy_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!phy_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (idx = 0; idx < NUM_BCM_SR_USB_COMBO_PHYS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) phy_cfg[idx].regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) phy_cfg[idx].version = version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) phy_cfg[idx].offset = bcm_usb_combo_phy_hs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) phy_cfg[idx].type = USB_HS_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) phy_cfg[idx].offset = bcm_usb_combo_phy_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) phy_cfg[idx].type = USB_SS_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) phy_cfg[idx].phy = devm_phy_create(dev, node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) &sr_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (IS_ERR(phy_cfg[idx].phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return PTR_ERR(phy_cfg[idx].phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) phy_set_drvdata(phy_cfg[idx].phy, &phy_cfg[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else if (version == BCM_SR_USB_HS_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) phy_cfg = devm_kzalloc(dev, sizeof(struct bcm_usb_phy_cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!phy_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) phy_cfg->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) phy_cfg->version = version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) phy_cfg->offset = bcm_usb_hs_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) phy_cfg->type = USB_HS_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) phy_cfg->phy = devm_phy_create(dev, node, &sr_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (IS_ERR(phy_cfg->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return PTR_ERR(phy_cfg->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) phy_set_drvdata(phy_cfg->phy, phy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_set_drvdata(dev, phy_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct of_device_id bcm_usb_phy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .compatible = "brcm,sr-usb-combo-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .data = (void *)BCM_SR_USB_COMBO_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .compatible = "brcm,sr-usb-hs-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .data = (void *)BCM_SR_USB_HS_PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DEVICE_TABLE(of, bcm_usb_phy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int bcm_usb_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct device_node *dn = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enum bcm_usb_phy_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct phy_provider *phy_provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) of_id = of_match_node(bcm_usb_phy_of_match, dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) version = (enum bcm_usb_phy_version)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = bcm_usb_phy_create(dev, dn, regs, version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) phy_provider = devm_of_phy_provider_register(dev, bcm_usb_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return PTR_ERR_OR_ZERO(phy_provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct platform_driver bcm_usb_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = "phy-bcm-sr-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .of_match_table = bcm_usb_phy_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .probe = bcm_usb_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) module_platform_driver(bcm_usb_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_AUTHOR("Broadcom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DESCRIPTION("Broadcom stingray USB Phy driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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