^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016-2018 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* we have up to 8 PAXB based RC. The 9th one is always PAXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SR_NR_PCIE_PHYS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCIE_PIPEMUX_CFG_OFFSET 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIE_PIPEMUX_SELECT_STRAP 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCIE_PIPEMUX_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIE_PIPEMUX_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MHB_MEM_PW_PAXC_OFFSET 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MHB_PWR_ARR_POWERON 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MHB_PWR_ARR_POWEROK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MHB_PWR_POWERON 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MHB_PWR_POWEROK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MHB_PWR_STATUS_MASK (MHB_PWR_ARR_POWERON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MHB_PWR_ARR_POWEROK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MHB_PWR_POWERON | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MHB_PWR_POWEROK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct sr_pcie_phy_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct sr_pcie_phy - Stingray PCIe PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @core: pointer to the Stingray PCIe PHY core control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @index: PHY index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @phy: pointer to the kernel PHY device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct sr_pcie_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct sr_pcie_phy_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * struct sr_pcie_phy_core - Stingray PCIe PHY core control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @base: base register of PCIe SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @cdru: regmap to the CDRU device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @mhb: regmap to the MHB device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pipemux: pipemuex strap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @phys: array of PCIe PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct sr_pcie_phy_core {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct regmap *cdru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct regmap *mhb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 pipemux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct sr_pcie_phy phys[SR_NR_PCIE_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * PCIe PIPEMUX lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Each array index represents a PIPEMUX strap setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * The array element represents a bitmap where a set bit means the PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * core and associated serdes has been enabled as RC and is available for use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const u8 pipemux_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* PIPEMUX = 0, EP 1x16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* PIPEMUX = 2, EP 4x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0x81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0xc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* PIPEMUX = 5, RC 8x2, all 8 cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0xcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0xfd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Return true if the strap setting is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static bool pipemux_strap_is_valid(u32 pipemux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return !!(pipemux < ARRAY_SIZE(pipemux_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Read the PCIe PIPEMUX from strap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 pipemux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Read PIPEMUX configuration register to determine the pipemux setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * In the case when the value indicates using HW strap, fall back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * use HW strap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pipemux &= PCIE_PIPEMUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) regmap_read(core->cdru, CDRU_STRAP_DATA_LSW_OFFSET, &pipemux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pipemux >>= PCIE_PIPEMUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pipemux &= PCIE_PIPEMUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return pipemux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Given a PIPEMUX strap and PCIe core index, this function returns true if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * PCIe core needs to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static bool pcie_core_is_for_rc(struct sr_pcie_phy *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct sr_pcie_phy_core *core = phy->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int core_idx = phy->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return !!((pipemux_table[core->pipemux] >> core_idx) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int sr_pcie_phy_init(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sr_pcie_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Check whether this PHY is for root complex or not. If yes, return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * zero so the host driver can proceed to enumeration. If not, return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * an error and that will force the host driver to bail out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (pcie_core_is_for_rc(phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int sr_paxc_phy_init(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sr_pcie_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sr_pcie_phy_core *core = phy->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int core_idx = phy->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (core_idx != SR_PAXC_PHY_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regmap_read(core->mhb, MHB_MEM_PW_PAXC_OFFSET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(core->dev, "PAXC is not powered up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct phy_ops sr_pcie_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .init = sr_pcie_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct phy_ops sr_paxc_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .init = sr_paxc_phy_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct phy *sr_pcie_phy_xlate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct of_phandle_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct sr_pcie_phy_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int phy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) core = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) phy_idx = args->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (WARN_ON(phy_idx >= SR_NR_PCIE_PHYS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return core->phys[phy_idx].phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int sr_pcie_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct sr_pcie_phy_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int phy_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) core->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) core->base = devm_ioremap_resource(core->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (IS_ERR(core->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return PTR_ERR(core->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) core->cdru = syscon_regmap_lookup_by_phandle(node, "brcm,sr-cdru");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (IS_ERR(core->cdru)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(core->dev, "unable to find CDRU device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return PTR_ERR(core->cdru);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) core->mhb = syscon_regmap_lookup_by_phandle(node, "brcm,sr-mhb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (IS_ERR(core->mhb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(core->dev, "unable to find MHB device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return PTR_ERR(core->mhb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* read the PCIe PIPEMUX strap setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) core->pipemux = pipemux_strap_read(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!pipemux_strap_is_valid(core->pipemux)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(core->dev, "invalid PCIe PIPEMUX strap %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) core->pipemux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (phy_idx = 0; phy_idx < SR_NR_PCIE_PHYS; phy_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct sr_pcie_phy *p = &core->phys[phy_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const struct phy_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (phy_idx == SR_PAXC_PHY_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ops = &sr_paxc_phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ops = &sr_pcie_phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) p->phy = devm_phy_create(dev, NULL, ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(p->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(dev, "failed to create PCIe PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return PTR_ERR(p->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) p->core = core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) p->index = phy_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) phy_set_drvdata(p->phy, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_set_drvdata(dev, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) provider = devm_of_phy_provider_register(dev, sr_pcie_phy_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (IS_ERR(provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(dev, "failed to register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_info(dev, "Stingray PCIe PHY driver initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct of_device_id sr_pcie_phy_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .compatible = "brcm,sr-pcie-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_DEVICE_TABLE(of, sr_pcie_phy_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct platform_driver sr_pcie_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "sr-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .of_match_table = sr_pcie_phy_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .probe = sr_pcie_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) module_platform_driver(sr_pcie_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR("Ray Jui <ray.jui@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DESCRIPTION("Broadcom Stingray PCIe PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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