^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIE_CFG_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIE1_PHY_IDDQ_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCIE0_PHY_IDDQ_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum cygnus_pcie_phy_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) CYGNUS_PHY_PCIE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) CYGNUS_PHY_PCIE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MAX_NUM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct cygnus_pcie_phy_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * struct cygnus_pcie_phy - Cygnus PCIe PHY device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @core: pointer to the Cygnus PCIe PHY core control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @id: internal ID to identify the Cygnus PCIe PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @phy: pointer to the kernel PHY device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct cygnus_pcie_phy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct cygnus_pcie_phy_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum cygnus_pcie_phy_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @base: base register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @lock: mutex to protect access to individual PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @phys: pointer to Cygnus PHY device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct cygnus_pcie_phy_core {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct cygnus_pcie_phy phys[MAX_NUM_PHYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct cygnus_pcie_phy_core *core = phy->core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) mutex_lock(&core->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) switch (phy->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case CYGNUS_PHY_PCIE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) shift = PCIE0_PHY_IDDQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case CYGNUS_PHY_PCIE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) shift = PCIE1_PHY_IDDQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mutex_unlock(&core->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val = readl(core->base + PCIE_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) val &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(val, core->base + PCIE_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Wait 50 ms for the PCIe Serdes to stabilize after the analog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * front end is brought up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = readl(core->base + PCIE_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) val |= BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(val, core->base + PCIE_CFG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mutex_unlock(&core->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enable ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int cygnus_pcie_phy_power_on(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return cygnus_pcie_power_config(phy, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int cygnus_pcie_phy_power_off(struct phy *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return cygnus_pcie_power_config(phy, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct phy_ops cygnus_pcie_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .power_on = cygnus_pcie_phy_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .power_off = cygnus_pcie_phy_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int cygnus_pcie_phy_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct device_node *node = dev->of_node, *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct cygnus_pcie_phy_core *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct phy_provider *provider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (of_get_child_count(node) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_err(dev, "PHY no child node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) core->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) core->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (IS_ERR(core->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return PTR_ERR(core->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mutex_init(&core->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for_each_available_child_of_node(node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct cygnus_pcie_phy *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (of_property_read_u32(child, "reg", &id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(dev, "missing reg property for %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (id >= MAX_NUM_PHYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(dev, "invalid PHY id: %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (core->phys[id].phy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(dev, "duplicated PHY id: %u\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) p = &core->phys[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (IS_ERR(p->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(dev, "failed to create PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = PTR_ERR(p->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto put_child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) p->core = core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) p->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) phy_set_drvdata(p->phy, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_set_drvdata(dev, core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (IS_ERR(provider)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, "failed to register PHY provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return PTR_ERR(provider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) put_child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct of_device_id cygnus_pcie_phy_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .compatible = "brcm,cygnus-pcie-phy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct platform_driver cygnus_pcie_phy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .name = "cygnus-pcie-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .of_match_table = cygnus_pcie_phy_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .probe = cygnus_pcie_phy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) module_platform_driver(cygnus_pcie_phy_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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